An Overview of the 386 Internal Architecture
Figure 5-1 on page 41 illustrates the internal architecture of the 386 processor. It consisted of the following internal units:
Bus Unit. Interfaces the processor to the FSB and the system in general.
Prefetcher. Working on the presumption that the currently executing program never executes jumps, it instructs the Bus Unit to perform a series of memory code read transactions from ascending memory addresses.
Prefetch Queue. The instructions prefetched from memory are placed in this queue.
Instruction Decoder. Decodes each instruction into an executable form.
Instruction Queue. The decoded instructions are placed in this queue.
Execution Unit. Executes instructions one at a time as they are provided ...
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