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The System Designer’s Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling

Book Description

The demand is exploding for complete, integrated systems that sense, process, manipulate, and control complex entities such as sound, images, text, motion, and environmental conditions. These systems, from hand-held devices to automotive sub-systems to aerospace vehicles, employ electronics to manage and adapt to a world that is, predominantly, neither digital nor electronic. To respond to this design challenge, the industry has developed and standardized VHDL-AMS, a unified design language for modeling digital, analog, mixed-signal, and mixed-technology systems. VHDL-AMS extends VHDL to bring the successful HDL modeling methodology of digital electronic systems design to these new design disciplines. Gregory Peterson and Darrell Teegarden join best-selling author Peter Ashenden in teaching designers how to use VHDL-AMS to model these complex systems. This comprehensive tutorial and reference provides detailed descriptions of both the syntax and semantics of the language and of successful modeling techniques. It assumes no previous knowledge of VHDL, but instead teaches VHDL and VHDL-AMS in an integrated fashion, just as it would be used by designers of these complex, integrated systems.

Table of Contents

  1. Copyright
    1. Dedication
  2. The Morgan Kaufmann Series in Systems on Silicon
  3. Preface
    1. Structure of the Book
    2. The Case Studies
      1. Case Study 1: Mixed-Signal Focus
      2. Case Study 2: Mixed-Technology Focus
      3. Case Study 3: Power Systems Focus
      4. Case Study 4: Communications System Focus
      5. Case Study 5: Full System Analysis
    3. Notes to Instructors
    4. CD-ROM
    5. Resources for Help and Information
    6. Acknowledgments
  4. One. Fundamental Concepts
    1. 1.1. Modeling Systems
    2. 1.2. Domains and Levels of Modeling
      1. Digital Modeling Example
      2. Analog Modeling Example
      3. Mixed-Signal Modeling Example
      4. Energy Domains and Conservation
    3. 1.3. Modeling Languages
    4. 1.4. VHDL-AMS Modeling Concepts
      1. Elements of Behavior
      2. Elements of Structure
      3. Mixed Structural and Behavioral Models
      4. Test Benches
      5. Analysis, Elaboration and Execution
    5. 1.5. Learning a New Language: Lexical Elements and Syntax
      1. Lexical Elements
        1. Comments
        2. Identifiers
        3. Reserved Words
        4. Special Symbols
        5. Numbers
        6. Characters
        7. Strings
        8. Bit Strings
      2. Syntax Descriptions
    6. Exercises
  5. Two. Scalar Data Types, Natures and Operations
    1. 2.1. Constants and Variables
      1. Constant and Variable Declarations
      2. Variable Assignment
    2. 2.2. Scalar Types
      1. Type Declarations
      2. Integer Types
      3. Floating-Point Types
      4. Physical Types
        1. Time
      5. Enumeration Types
        1. Characters
        2. Booleans
        3. Bits
        4. Standard Logic
    3. 2.3. Type Classification
      1. Subtypes
      2. Type Qualification
      3. Type Conversion
    4. 2.4. Scalar Natures
      1. Nature Declarations
      2. Standard Natures
      3. Subnatures
    5. 2.5. Attributes of Scalar Types and Natures
    6. 2.6. Expressions and Operators
    7. Exercises
  6. Three. Sequential Statements
    1. 3.1. If Statements
    2. 3.2. Case Statements
    3. 3.3. Null Statements
    4. 3.4. Loop Statements
      1. Exit Statements
      2. Next Statements
      3. While Loops
      4. For Loops
      5. Summary of Loop Statements
    5. 3.5. Assertion and Report Statements
    6. Exercises
  7. Four. Composite Data Types and Operations
    1. 4.1. Arrays
      1. Multidimensional Arrays
      2. Array Aggregates
      3. Array Attributes
    2. 4.2. Unconstrained Arrays
      1. Strings
      2. Real Vectors
      3. Bit Vectors
      4. Standard-Logic Arrays
      5. String and Bit-String Literals
      6. Unconstrained Array Ports
    3. 4.3. Array Operations and Referencing
      1. Array Slices
      2. Array Type Conversions
    4. 4.4. Records
      1. Record Aggregates
    5. Exercises
  8. Five. Digital Modeling Constructs
    1. 5.1. Entity Declarations
    2. 5.2. Architecture Bodies
      1. Concurrent Statements
      2. Signal Declarations
    3. 5.3. Digital Behavioral Descriptions
      1. Signal Assignment
      2. Signal Attributes
      3. Wait Statements
      4. Delta Delays
      5. Transport and Inertial Delay Mechanisms
      6. Process Statements
      7. Concurrent Signal Assignment Statements
        1. Conditional Signal Assignment Statements
        2. Selected Signal Assignment Statements
      8. Concurrent Assertion Statements
      9. Entities and Passive Processes
    4. 5.4. Digital Structural Descriptions
      1. Component Instantiation and Port Maps
    5. Exercises
  9. Six. Analog Modeling Constructs
    1. 6.1. Free Quantities
      1. Quantity Ports
    2. 6.2. Terminals and Branch Quantities
      1. Terminal Declarations
      2. Branch Quantity Declarations
      3. Terminal Ports
    3. 6.3. Attributes of Terminals and Quantities
      1. Attributes of Terminals
      2. Attributes of Quantities
        1. The Tolerance Attribute
        2. The Above Attribute
        3. The Delayed Attribute
        4. The Dot Attribute
        5. The Integ Attribute
        6. The Slew Attribute
      3. Quantity Attributes of Signals
        1. The Ramp Attribute
        2. The Slew Attribute
        3. Signal Initialization
    4. 6.4. Simultaneous Statements
      1. Simple Simultaneous Statement
      2. Simultaneous If Statement
      3. Simultaneous Case Statement
      4. Simultaneous Null Statement
    5. 6.5. Analog Structural Descriptions
    6. 6.6. Discontinuities and Break Statements
      1. Concurrent Break Statements
    7. 6.7. Step Limit Specifications
    8. 6.8. Mixed-Signal Descriptions
      1. Analog-to-Digital Conversion
      2. Digital-to-Analog Conversion
    9. 6.9. Mixed-Technology Descriptions
    10. Exercises
  10. Seven. Design Processing
    1. 7.1. Analysis
      1. Design Libraries, Library Clauses and Use Clauses
    2. 7.2. Elaboration
      1. Requirements for Solvability
    3. 7.3. Execution
    4. Exercises
  11. Eight. Case Study 1: Mixed-Signal Focus
    1. 8.1. System Overview
    2. 8.2. Command and Control System Design
      1. Control Sticks
      2. Digitize/Encode Block
        1. Analog Switch
        2. Analog-to-Digital Converter
        3. Encoder State Machine
      3. Decoder/Pulse-Width Block
      4. Pulse-Width/Analog Converter
        1. Digital-to-Analog Converter
    3. 8.3. Design Trade-Off Analysis
      1. Converter Accuracy
      2. System Analysis
    4. Exercises
  12. Nine. Subprograms
    1. 9.1. Procedures
      1. Return Statement in a Procedure
    2. 9.2. Procedure Parameters
      1. Signal Parameters
      2. Default Values
      3. Unconstrained Array Parameters
      4. Summary of Procedure Parameters
    3. 9.3. Concurrent Procedure Call Statements
    4. 9.4. Functions
      1. Functional Modeling
      2. Pure and Impure Functions
      3. Functions in Simultaneous Statements
      4. The Function Now
    5. 9.5. Simultaneous Procedural Statements
    6. 9.6. Overloading
      1. Overloading Operator Symbols
    7. 9.7. Visibility of Declarations
    8. Exercises
  13. Ten. Packages and Use Clauses
    1. 10.1. Package Declarations
      1. Subprograms in Package Declarations
      2. Constants in Package Declarations
    2. 10.2. Package Bodies
    3. 10.3. Use Clauses
    4. 10.4. The Predefined Package Standard
    5. 10.5. IEEE Standard Packages
      1. Std_Logic_1164 Multivalue Logic System
      2. Standard VHDL Synthesis Packages
      3. Standard VHDL Mathematical Packages
        1. Real Number Mathematical Package
        2. Complex Number Mathematical Package
      4. Proposed Standard Analog Packages
    6. Exercises
  14. Eleven. Aliases
    1. 11.1. Aliases for Data Objects
    2. 11.2. Aliases for Non-Data Items
    3. Exercises
  15. Twelve. Generic Constants
    1. 12.1. Parameterizing Behavior
    2. 12.2. Parameterizing Structure
    3. Exercises
  16. Thirteen. Frequency and Transfer Function Modeling
    1. 13.1. Frequency-Based Modeling
      1. Spectral Source Quantities
    2. 13.2. Noise Modeling
    3. 13.3. Laplace Transfer Functions
    4. 13.4. Discrete Transfer Functions and Sampling
      1. Zero-Order Hold (ZOH)
      2. Z Transfer Function (ZTF)
      3. Summary of Transfer Function Attributes
      4. Z-Domain Sampling
    5. Exercises
  17. Fourteen. Case Study 2: Mixed-Technology Focus
    1. 14.1. Rudder System Overview
      1. Rudder System Specifications and Development
    2. 14.2. S-Domain Implementation
      1. Servo Controller
        1. Two-Input Summer Model
        2. Limiter Model
      2. Motor Model
        1. Lag Model
      3. Gearbox
        1. Gain Model
        2. Integrator Model
      4. Rudder Load
      5. S-Domain System Performance
        1. Lead-Lag Compensator Model
    3. 14.3. Mixed Mechanical/S-Domain Implementation
      1. Servo/Amplifier
      2. Motor Model
      3. Gearbox
      4. Control Horn Assembly
      5. Rudder Model
    4. 14.4. Design Trade-Off Analysis
      1. Deriving Z-Domain Coefficients
      2. Implement Compensator as Difference Equations
    5. Exercises
  18. Fifteen. Resolved Signals
    1. 15.1. Basic Resolved Signals
      1. Composite Resolved Subtypes
      2. Summary of Resolved Subtypes
    2. 15.2. IEEE Std_Logic_1164 Resolved Subtypes
    3. 15.3. Resolved Signals and Ports
      1. Resolved Ports
      2. Driving Value Attribute
    4. 15.4. Resolved Signal Parameters
    5. Exercises
  19. Sixteen. Components and Configurations
    1. 16.1. Components
      1. Component Declarations
      2. Component Instantiation
      3. Packaging Components
    2. 16.2. Configuring Component Instances
      1. Basic Configuration Declarations
      2. Configuring Multiple Levels of Hierarchy
      3. Direct Instantiation of Configured Entities
      4. Generic and Port Maps in Configurations
      5. Deferred Component Binding
    3. 16.3. Configuration Specifications
      1. Incremental Binding
    4. Exercises
  20. Seventeen. Generate Statements
    1. 17.1. Generating Iterative Structures
    2. 17.2. Conditionally Generating Structures
      1. Recursive Structures
    3. 17.3. Configuration of Generate Statements
    4. Exercises
  21. Eighteen. Case Study 3: DC-DC Power Converter
    1. 18.1. Buck Converter Theory and Design
      1. Selecting a Switching Regulator Topology
    2. 18.2. Modeling with VHDL-AMS
      1. Capacitor Model
      2. Ideal Switch Model
    3. 18.3. Voltage-Mode Control
    4. 18.4. Averaged Model
    5. 18.5. Closing the Loop
      1. Compensation Design
      2. Load Regulation
      3. Line Regulation
    6. 18.6. Design Trade-Off Study
    7. Exercises
  22. Nineteen. Guards and Blocks
    1. 19.1. Guarded Signals and Disconnection
      1. The Driving Attribute
      2. Guarded Ports
      3. Guarded Signal Parameters
    2. 19.2. Blocks and Guarded Signal Assignment
      1. Explicit Guard Signals
      2. Disconnection Specifications
    3. 19.3. Using Blocks for Structural Modularity
      1. Generics and Ports in Blocks
      2. Configuring Designs with Blocks
    4. Exercises
  23. Twenty. Access Types and Abstract Data Types
    1. 20.1. Access Types
      1. Access Type Declarations and Allocators
      2. Assignment and Equality of Access Values
      3. Access Types for Records and Arrays
    2. 20.2. Linked Data Structures
      1. Deallocation and Storage Management
    3. 20.3. Abstract Data Types Using Packages
      1. Container ADTs
        1. An Ordered-Collection ADT
    4. Exercises
  24. Twenty-One. Files and Input/Output
    1. 21.1. Files
      1. File Declarations
      2. Reading from Files
      3. Writing to Files
      4. Files Declared in Subprograms
      5. Explicit Open and Close Operations
      6. File Parameters in Subprograms
      7. Portability of Files
    2. 21.2. The Package Textio
      1. Textio Read Operations
      2. Textio Write Operations
      3. Reading and Writing User-Defined Types
    3. Exercises
  25. Twenty-Two. Attributes and Groups
    1. 22.1. Predefined Attributes
      1. Attributes of Scalar Types
      2. Attributes of Scalar Natures
      3. Attributes of Array Types and Objects
      4. Attributes of Signals
      5. Attributes of Terminals
      6. Attributes of Quantities
      7. Attributes of Named Items
    2. 22.2. User-Defined Attributes
      1. Attribute Declarations
      2. Attribute Specifications
      3. The Attribute Foreign
    3. 22.3. Groups
    4. Exercises
  26. Twenty-Three. Case Study 4: Communication System
    1. 23.1. Communication System Overview
    2. 23.2. Frequency Shift Keying
    3. 23.3. FSK Detection
      1. Non-Coherent Detection
      2. Phase-Locked Loop Detection
    4. 23.4. Trade-Off Study
    5. Exercises
  27. Twenty-Four. Miscellaneous Topics
    1. 24.1. Buffer and Linkage Ports
    2. 24.2. Conversion Functions in Association Lists
    3. 24.3. Postponed Processes
    4. 24.4. Shared Variables
    5. Exercises
  28. Twenty-Five. Integrated System Modeling
    1. 25.1. Top-down Design
    2. 25.2. System Specification
    3. 25.3. Partitioning the System
    4. 25.4. Refining the Design
    5. 25.5. Model Calibration
    6. 25.6. System Verification
    7. 25.7. Synthesis and Reuse
    8. 25.8. Design Trade-Offs and Optimization
      1. Architectural Trade-Offs
      2. Parametric Analysis
      3. Optimization
      4. Response Surface Models
    9. Exercises
  29. Twenty-Six. Case Study 5: RC Airplane System
    1. 26.1. RC System Overview
    2. 26.2. Interfacing Command and Control to the Rudder System
    3. 26.3. System Power Supply Effects
      1. Supply Level and Servo Error
      2. Rudder Servo with Buck Converter
    4. 26.4. Propeller System
      1. Propeller System Performance
    5. 26.5. Human Controller
      1. Modeling the Human
      2. System Accuracy
    6. 26.6. Summary
    7. Exercises
  30. A. Using SPICE Models in VHDL-AMS
    1. A.1. SystemVision/ADMS (Mentor Graphics Corporation)
      1. VHDL-AMS Model with SPICE Component
      2. SPICE Model with VHDL-AMS Component
    2. A.2. VeriasHDL (Synopsys, Inc.)
      1. The HSPICE Library
      2. VHDL-AMS Hierarchies
      3. HSPICE Net-Lists
    3. A.3. Auriga (FTL Systems, Inc.)
  31. B. The Predefined Package Standard
  32. C. IEEE Standard Packages
    1. C.1. Std_Logic_1164 Multivalue Logic System
    2. C.2. Standard 1076.2 VHDL Mathematical Packages
      1. Real Mathematical Operations
      2. Complex Mathematical Operations
  33. D. Related Standards
    1. D.1. IEEE VHDL Standards
      1. IEEE Standard 1076 VHDL
      2. VHDL Programming Language Interface
      3. IEEE Standard 1076.1 VHDL-AMS
      4. VHDL-AMS Programming Language Interface
      5. IEEE Standard 1076.2 Mathematical Packages
      6. IEEE Standard 1076.3 Synthesis Packages
      7. IEEE Standard 1076.4 VITAL
      8. IEEE P1076.5 VHDL Utility Library
      9. IEEE 1076.6 VHDL Synthesis Interoperability
      10. IEEE Standard 1164 Multivalue Logic System
      11. IEEE Standard 1029.1 WAVES
    2. D.2. Other Design Automation Standards
      1. IEEE Standard 1364 Verilog
      2. IEEE P1364.1 Verilog Synthesis Interoperability
      3. OVI Verilog-AMS
      4. IEEE Standard 1499 OMF
      5. Rosetta
      6. IEEE P1497 Standard Delay Format
      7. IEEE P1603 Advanced Library Format
      8. IEEE Standard 1481 Delay and Power Calculation
      9. EIA-682 Electronic Design Interchange Format (EDIF)
      10. EIA-567-A Component Modeling and Interface
      11. EIA/IS-103-A Library of Parameterized Modules
  34. E. VHDL-AMS Syntax
    1. Index to Syntax Rules
    2. E.1. Design File
    3. E.2. Library Unit Declarations
    4. E.3. Declarations and Specifications
    5. E.4. Type Definitions
    6. E.5. Concurrent Statements
    7. E.6. Simultaneous Statements
    8. E.7. Sequential Statements
    9. E.8. Interfaces and Associations
    10. E.9. Expressions
  35. F. Answers to Exercises
    1. Chapter 1
    2. Chapter 2
    3. Chapter 3
    4. Chapter 4
    5. Chapter 5
    6. Chapter 6
    7. Chapter 7
    8. Chapter 8
    9. Chapter 9
    10. Chapter 10
    11. Chapter 11
    12. Chapter 12
    13. Chapter 13
    14. Chapter 14
    15. Chapter 15
    16. Chapter 16
    17. Chapter 17
    18. Chapter 18
    19. Chapter 19
    20. Chapter 20
    21. Chapter 21
    22. Chapter 22
    23. Chapter 23
    24. Chapter 24
    25. Chapter 25
    26. Chapter 26
  36. G. CD-ROM Guide
    1. Contents of the CD-ROM
    2. Source Code Files
    3. Educational Library of Models
  37. References
  38.