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The Designer's Guide to VHDL

Book Description



Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.


VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.


This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.

* Details how the new standard allows for increased portability across tools.
* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.

Table of Contents

  1. Cover
  2. Title Page
  3. Copyright
  4. Dedication
  5. Foreword
  6. Foreword to the First Edition
  7. Preface
  8. Table of Contents
  9. Chapter 1: Fundamental Concepts
    1. 1.1 Modeling Digital Systems
    2. 1.2 Domains and Levels of Modeling
    3. 1.3 Modeling Languages
    4. 1.4 VHDL Modeling Concepts
    5. 1.5 Learning a New Language: Lexical Elements and Syntax
  10. Chapter 2: Scalar Data Types and Operations
    1. 2.1 Constants and Variables
    2. 2.2 Scalar Types
    3. 2.3 Type Classification
    4. 2.4 Attributes of Scalar Types
    5. 2.5 Expressions and Operators
  11. Chapter 3: Sequential Statements
    1. 3.1 If Statements
    2. 3.2 Case Statements
    3. 3.3 Null Statements
    4. 3.4 Loop Statements
    5. 3.5 Assertion and Report Statements
  12. Chapter 4: Composite Data Types and Operations
    1. 4.1 Arrays
    2. 4.2 Unconstrained Array Types
    3. 4.3 Array Operations and Referencing
    4. 4.4 Records
  13. Chapter 5: Basic Modeling Constructs
    1. 5.1 Entity Declarations
    2. 5.2 Architecture Bodies
    3. 5.3 Behavioral Descriptions
    4. 5.4 Structural Descriptions
    5. 5.5 Design Processing
  14. Chapter 6: Case Study: A Pipelined Multiplier Accumulator
    1. 6.1 Algorithm Outline
    2. 6.2 A Behavioral Model
    3. 6.3 A Register-Transfer-Level Model
  15. Chapter 7: Subprograms
    1. 7.1 Procedures
    2. 7.2 Procedure Parameters
    3. 7.3 Concurrent Procedure Call Statements
    4. 7.4 Functions
    5. 7.5 Overloading
    6. 7.6 Visibility of Declarations
  16. Chapter 8: Packages and Use Clauses
    1. 8.1 Package Declarations
    2. 8.2 Package Bodies
    3. 8.3 Use Clauses
    4. 8.4 The Predefined Package Standard
    5. 8.5 IEEE Standard Packages
  17. Chapter 9: Aliases
    1. 9.1 Aliases for Data Objects
    2. 9.2 Aliases for Non-Data Items
  18. Chapter 10: Case Study: A Bit-Vector Arithmetic Package
    1. 10.1 The Package Interface
    2. 10.2 The Package Body
    3. 10.3 An ALU Using the Arithmetic Package
  19. Chapter 11: Resolved Signals
    1. 11.1 Basic Resolved Signals
    2. 11.2 IEEE Std_Logic_1164 Resolved Subtypes
    3. 11.3 Resolved Signals and Ports
    4. 11.4 Resolved Signal Parameters
  20. Chapter 12: Generic Constants
    1. 12.1 Parameterizing Behavior
    2. 12.2 Parameterizing Structure
  21. Chapter 13: Components and Configurations
    1. 13.1 Components
    2. 13.2 Configuring Component Instances
    3. 13.3 Configuration Specifications
  22. Chapter 14: Generate Statements
    1. 14.1 Generating Iterative Structures
    2. 14.2 Conditionally Generating Structures
    3. 14.3 Configuration of Generate Statements
  23. Chapter 15: Case Study: The DLX Computer System
    1. 15.1 Overview of the DLX CPU
    2. 15.2 A Behavioral Model
    3. 15.3 Testing the Behavioral Model
    4. 15.4 A Register-Transfer-Level Model
    5. 15.5 Testing the Register-Transfer-Level Model
  24. Chapter 16: Guards and Blocks
    1. 16.1 Guarded Signals and Disconnection
    2. 16.2 Blocks and Guarded Signal Assignment
    3. 16.3 Using Blocks for Structural Modularity
  25. Chapter 17: Access Types and Abstract Data Types
    1. 17.1 Access Types
    2. 17.2 Linked Data Structures
    3. 17.3 Abstract Data Types Using Packages
  26. Chapter 18: Files and Input/Output
    1. 18.1 Files
    2. 18.2 The Package Textio
  27. Chapter 19: Case Study: Queuing Networks
    1. 19.1 Queuing Network Concepts
    2. 19.2 Queuing Network Modules
    3. 19.3 A Queuing Network for a Disk System
  28. Chapter 20: Attributes and Groups
    1. 20.1 Predefined Attributes
    2. 20.2 User-Defined Attributes
    3. 20.3 Groups
  29. Chapter 21: Miscellaneous Topics
    1. 21.1 Buffer and Linkage Ports
    2. 21.2 Conversion Functions in Association Lists
    3. 21.3 Postponed Processes
    4. 21.4 Shared Variables
  30. A: Synthesis
  31. B: The Predefined Package Standard
  32. C: IEEE Standard Packages
  33. D: Related Standards
  34. E: VHDL Syntax
  35. F: Differences among VHDL-87, VHDL-93 and VHDL-2001
  36. G: Answers to Exercises
  37. References
  38. Index