Since the main purpose of a model written in VHDL is to describe a hardware design, it should be made as easy as possible to read and understand. In this chapter, we introduce aliases as a means of making a model clearer. As in everyday use, an alias is simply an alternate name for something. We see how we can use aliases in VHDL for both data objects and other kinds of items that do not represent data in a model.
If we have a model that includes a data object, such as a constant, a variable, a signal or, as we see in a later chapter, a file, we can declare an alias for the object with an alias declaration. A simplified syntax rule for this is
alias_declaration ⇐ alias identifier is name ;
An alias declaration ...