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The Designer’s Guide to VHDL, Third Edition by Peter Ashenden

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Chapter 10. Case Study: A Pipelined Multiplier Accumulator

Now that we have covered the basic modeling facilities provided by VHDL, we will work through our first case study, the design of a pipelined multiplier accumulator (MAC) for a stream of complex numbers. Many digital signal processing algorithms, such as digital demodulation, filtering and equalization, make use of MACs. We use this design exercise to bring together concepts and techniques introduced in previous chapters.

Algorithm Outline

A complex MAC operates on two sequences of complex numbers, {xi} and {yi}. The MAC multiplies corresponding elements of the sequences and accumulates the sum of the products. The result is

where N is the length of the sequences. Each complex number is represented ...

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