Chapter 7. Packages and Use Clauses
Packages in VHDL provide an important way of organizing the data and subprograms declared in a model. In this chapter, we describe the basics of packages and show how they may be used. We will return to packages in Chapter 12, where we will see how they can be extended to make them more reusable than the basic form we discuss here.
Package Declarations
A VHDL package is simply a way of grouping a collection of related declarations that serve a common purpose. They might be a set of subprograms that provide operations on a particular type of data, or they might just be the set of declarations needed to model a particular design. The important thing is that they can be collected together into a separate design unit ...
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