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The Designer’s Guide to VHDL, Third Edition

Book Description

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

Table of Contents

  1. Copyright
    1. Dedication
  2. Preface
    1. Structure of the Book
    2. Changes in the Second and Third Editions
    3. Resources for Help and Information
    4. Acknowledgments
  3. 1. Fundamental Concepts
    1. 1.1. Modeling Digital Systems
    2. 1.2. Domains and Levels of Modeling
      1. 1.2.1. Modeling Example
    3. 1.3. Modeling Languages
    4. 1.4. VHDL Modeling Concepts
      1. 1.4.1. Elements of Behavior
      2. 1.4.2. Elements of Structure
      3. 1.4.3. Mixed Structural and Behavioral Models
      4. 1.4.4. Test Benches
      5. 1.4.5. Analysis, Elaboration and Execution
    5. 1.5. Learning a New Language: Lexical Elements and Syntax
      1. 1.5.1. Lexical Elements
        1. Comments
        2. Identifiers
        3. Reserved Words
        4. Special Symbols
        5. Numbers
        6. Characters
        7. Strings
        8. Bit Strings
      2. 1.5.2. Syntax Descriptions
    6. Exercises
  4. 2. Scalar Data Types and Operations
    1. 2.1. Constants and Variables
      1. 2.1.1. Constant and Variable Declarations
      2. 2.1.2. Variable Assignment
    2. 2.2. Scalar Types
      1. 2.2.1. Type Declarations
      2. 2.2.2. Integer Types
      3. 2.2.3. Floating-Point Types
      4. 2.2.4. Physical Types
        1. Time
      5. 2.2.5. Enumeration Types
        1. Characters
        2. Booleans
        3. Bits
        4. Standard Logic
        5. Condition Conversion
    3. 2.3. Type Classification
      1. 2.3.1. Subtypes
      2. 2.3.2. Type Qualification
      3. 2.3.3. Type Conversion
    4. 2.4. Attributes of Scalar Types
    5. 2.5. Expressions and Predefined Operations
    6. Exercises
  5. 3. Sequential Statements
    1. 3.1. If Statements
      1. 3.1.1. Conditional Variable Assignments
    2. 3.2. Case Statements
      1. 3.2.1. Selected Variable Assignments
    3. 3.3. Null Statements
    4. 3.4. Loop Statements
      1. 3.4.1. Exit Statements
      2. 3.4.2. Next Statements
      3. 3.4.3. While Loops
      4. 3.4.4. For Loops
      5. 3.4.5. Summary of Loop Statements
    5. 3.5. Assertion and Report Statements
    6. Exercises
  6. 4. Composite Data Types and Operations
    1. 4.1. Arrays
      1. 4.1.1. Multidimensional Arrays
      2. 4.1.2. Array Aggregates
      3. 4.1.3. Array Attributes
    2. 4.2. Unconstrained Array Types
      1. 4.2.1. Predefined Array Types
        1. Strings
        2. Boolean Vectors, Integer Vectors, Real Vectors, and Time Vectors
        3. Bit Vectors
        4. Standard-Logic Arrays
        5. String and Bit-String Literals
      2. 4.2.2. Unconstrained Array Element Types
      3. 4.2.3. Unconstrained Array Ports
    3. 4.3. Array Operations and Referencing
      1. 4.3.1. Logical Operators
      2. 4.3.2. Shift Operators
      3. 4.3.3. Relational Operators
        1. Maximum and Minimum Operations
      4. 4.3.4. The Concatenation Operator
      5. 4.3.5. To_String Operations
      6. 4.3.6. Array Slices
      7. 4.3.7. Array Type Conversions
      8. 4.3.8. Arrays in Case Statements
      9. 4.3.9. Matching Case Statements
        1. Matching Selected Variable Assignments
    4. 4.4. Records
      1. 4.4.1. Record Aggregates
      2. 4.4.2. Unconstrained Record Element Types
    5. Exercises
  7. 5. Basic Modeling Constructs
    1. 5.1. Entity Declarations and Architecture Bodies
      1. 5.1.1. Concurrent Statements
      2. 5.1.2. Signal Declarations
    2. 5.2. Behavioral Descriptions
      1. 5.2.1. Signal Assignment
        1. Conditional Signal Assignments
        2. Selected Signal Assignments
      2. 5.2.2. Signal Attributes
      3. 5.2.3. Wait Statements
      4. 5.2.4. Delta Delays
      5. 5.2.5. Transport and Inertial Delay Mechanisms
      6. 5.2.6. Process Statements
      7. 5.2.7. Concurrent Signal Assignment Statements
        1. Concurrent Simple Signal Assignments
        2. Concurrent Conditional Signal Assignment
        3. Concurrent Selected Signal Assignments
      8. 5.2.8. Concurrent Assertion Statements
      9. 5.2.9. Entities and Passive Processes
    3. 5.3. Structural Descriptions
    4. 5.4. Design Processing
      1. 5.4.1. Analysis
      2. 5.4.2. Design Libraries and Contexts
        1. Context Declarations
      3. 5.4.3. Elaboration
      4. 5.4.4. Execution
    5. Exercises
  8. 6. Subprograms
    1. 6.1. Procedures
      1. 6.1.1. Return Statement in a Procedure
    2. 6.2. Procedure Parameters
      1. 6.2.1. Signal Parameters
      2. 6.2.2. Default Values
      3. 6.2.3. Unconstrained Array Parameters
      4. 6.2.4. Summary of Procedure Parameters
    3. 6.3. Concurrent Procedure Call Statements
    4. 6.4. Functions
      1. 6.4.1. Functional Modeling
      2. 6.4.2. Pure and Impure Functions
      3. 6.4.3. The Function now
    5. 6.5. Overloading
      1. 6.5.1. Overloading Operator Symbols
    6. 6.6. Visibility of Declarations
    7. Exercises
  9. 7. Packages and Use Clauses
    1. 7.1. Package Declarations
      1. 7.1.1. Subprograms in Package Declarations
      2. 7.1.2. Constants in Package Declarations
    2. 7.2. Package Bodies
      1. 7.2.1. Local Packages
    3. 7.3. Use Clauses
      1. 7.3.1. Visibility of Used Declarations
    4. Exercises
  10. 8. Resolved Signals
    1. 8.1. Basic Resolved Signals
      1. 8.1.1. Composite Resolved Subtypes
      2. 8.1.2. Summary of Resolved Subtypes
      3. 8.1.3. IEEE std_logic_1164 Resolved Subtypes
    2. 8.2. Resolved Signals, Ports, and Parameters
      1. 8.2.1. Resolved Ports
      2. 8.2.2. Driving Value Attribute
      3. 8.2.3. Resolved Signal Parameters
    3. Exercises
  11. 9. Predefined and Standard Packages
    1. 9.1. The Predefined Packages standard and env
    2. 9.2. IEEE Standard Packages
      1. 9.2.1. Standard VHDL Mathematical Packages
        1. Real Number Mathematical Package
        2. Complex Number Mathematical Package
      2. 9.2.2. The std_logic_1164 Multivalue Logic System
      3. 9.2.3. Standard Integer Numeric Packages
      4. 9.2.4. Standard Fixed-Point Packages
      5. 9.2.5. Standard Floating-Point Packages
      6. 9.2.6. Package Summary
        1. Operator Overloading Summary
        2. Conversion Function Summary
        3. Strength Reduction Function Summary
    3. Exercises
  12. 10. Case Study: A Pipelined Multiplier Accumulator
    1. 10.1. Algorithm Outline
    2. 10.2. A Behavioral Model
      1. 10.2.1. Testing the Behavioral Model
    3. 10.3. A Register-Transfer-Level Model
      1. 10.3.1. Testing the Register-Transfer-Level Model
    4. Exercises
  13. 11. Aliases
    1. 11.1. Aliases for Data Objects
    2. 11.2. Aliases for Non-Data Items
    3. Exercises
  14. 12. Generics
    1. 12.1. Generic Constants
    2. 12.2. Generic Types
    3. 12.3. Generic Lists in Packages
      1. 12.3.1. Local Packages
      2. 12.3.2. Abstract Data Types Using Packages
    4. 12.4. Generic Lists in Subprograms
    5. 12.5. Generic Subprograms
    6. 12.6. Generic Packages
    7. Exercises
  15. 13. Components and Configurations
    1. 13.1. Components
      1. 13.1.1. Component Declarations
      2. 13.1.2. Component Instantiation
      3. 13.1.3. Packaging Components
    2. 13.2. Configuring Component Instances
      1. 13.2.1. Basic Configuration Declarations
      2. 13.2.2. Configuring Multiple Levels of Hierarchy
      3. 13.2.3. Direct Instantiation of Configured Entities
      4. 13.2.4. Generic and Port Maps in Configurations
      5. 13.2.5. Deferred Component Binding
    3. 13.3. Configuration Specifications
      1. 13.3.1. Incremental Binding
    4. Exercises
  16. 14. Generate Statements
    1. 14.1. Generating Iterative Structures
    2. 14.2. Conditionally Generating Structures
      1. 14.2.1. Recursive Structures
    3. 14.3. Configuration of Generate Statements
    4. Exercises
  17. 15. Access Types
    1. 15.1. Access Types
      1. 15.1.1. Access Type Declarations and Allocators
      2. 15.1.2. Assignment and Equality of Access Values
      3. 15.1.3. Access Types for Records and Arrays
    2. 15.2. Linked Data Structures
      1. 15.2.1. Deallocation and Storage Management
    3. 15.3. An Ordered-Dictionary ADT Using Access Types
    4. Exercises
  18. 16. Files and Input/Output
    1. 16.1. Files
      1. 16.1.1. File Declarations
      2. 16.1.2. Reading from Files
      3. 16.1.3. Writing to Files
      4. 16.1.4. Files Declared in Subprograms
      5. 16.1.5. Explicit Open and Close Operations
      6. 16.1.6. File Parameters in Subprograms
      7. 16.1.7. Portability of Files
    2. 16.2. The Package Textio
      1. 16.2.1. Textio Read Operations
      2. 16.2.2. Textio Write Operations
      3. 16.2.3. Reading and Writing Other Types
        1. Standard Package Read and Write Operations
    3. Exercises
  19. 17. Case Study: A Package for Memories
    1. 17.1. The Memories Package
    2. 17.2. Using the Memories Package
      1. 17.2.1. Common Address and Data Conversions
    3. Exercises
  20. 18. Test Bench and Verification Features
    1. 18.1. External Names
    2. 18.2. Force and Release Assignments
    3. 18.3. Embedded PSL in VHDL
    4. Exercises
  21. 19. Shared Variables and Protected Types
    1. 19.1. Shared Variables and Mutual Exclusion
    2. 19.2. Uninstantiated Methods in Protected Types
    3. Exercises
  22. 20. Attributes and Groups
    1. 20.1. Predefined Attributes
      1. 20.1.1. Attributes of Scalar Types
      2. 20.1.2. Attributes of Array Types and Objects
      3. 20.1.3. Attributes Giving Types
      4. 20.1.4. Attributes of Signals
      5. 20.1.5. Attributes of Named Items
    2. 20.2. User-Defined Attributes
      1. 20.2.1. Attribute Declarations
      2. 20.2.2. Attribute Specifications
    3. 20.3. Groups
    4. Exercises
  23. 21. Design for Synthesis
    1. 21.1. Synthesizable Subsets
    2. 21.2. Use of Data Types
      1. 21.2.1. Scalar Types
      2. 21.2.2. Composite and Other Types
    3. 21.3. Interpretation of Standard Logic Values
    4. 21.4. Modeling Combinational Logic
    5. 21.5. Modeling Sequential Logic
      1. 21.5.1. Modeling Edge-Triggered Logic
      2. 21.5.2. Level-Sensitive Logic and Inferring Storage
      3. 21.5.3. Modeling State Machines
    6. 21.6. Modeling Memories
    7. 21.7. Synthesis Attributes
    8. 21.8. Metacomments
    9. Exercises
  24. 22. Case Study: System Design Using the Gumnut Core
    1. 22.1. Overview of the Gumnut
      1. 22.1.1. Instruction Set Architecture
      2. 22.1.2. External Interface
        1. The Gumnut Entity Declaration
        2. Instruction and Data Memories
    2. 22.2. A Behavioral Model
      1. 22.2.1. The Gumnut Definitions Package
      2. 22.2.2. The Gumnut Behavioral Architecture Body
        1. Overview of the Interpreter
        2. Resetting the Interpreter
        3. Acknowledging an Interrupt
        4. Fetching an Instruction
        5. Performing an Arithmetic/Logical Operation
        6. Performing a Shift Operation
        7. Performing a Memory-I/O Instruction
        8. Performing a Branch Instruction
        9. Performing a Jump Instruction
        10. Performing a Miscellaneous Instruction
      3. 22.2.3. Verifying the Behavioral Model
    3. 22.3. A Register-Transfer-Level Model
      1. 22.3.1. The Architecture Body
      2. 22.3.2. Verifying the RTL Model
    4. 22.4. A Digital Alarm Clock
      1. 22.4.1. System Design
      2. 22.4.2. Synthesizing and Implementing the Alarm Clock
    5. Exercises
  25. 23. Miscellaneous Topics
    1. 23.1. Guards and Blocks
      1. 23.1.1. Guarded Signals and Disconnection
        1. The Driving Attribute
        2. Guarded Ports
        3. Guarded Signal Parameters
      2. 23.1.2. Blocks and Guarded Signal Assignment
        1. Explicit Guard Signals
        2. Disconnection Specifications
      3. 23.1.3. Using Blocks for Structural Modularity
        1. External Names and Blocks
        2. Generics and Ports in Blocks
        3. Configuring Designs with Blocks
    2. 23.2. IP Encryption
      1. 23.2.1. Key Exchange
    3. 23.3. VHDL Procedural Interface (VHPI)
      1. 23.3.1. Direct Binding
      2. 23.3.2. Tabular Registration and Indirect Binding
      3. 23.3.3. Registration of Applications and Libraries
    4. 23.4. Postponed Processes
    5. 23.5. Conversion Functions in Association Lists
    6. 23.6. Linkage Ports
    7. Exercises
  26. A. Standard Packages
    1. A.1. The Predefined Package standard
    2. A.2. The Predefined Package env
    3. A.3. The Predefined Package textio
    4. A.4. Standard VHDL Mathematical Packages
      1. A.4.1. The math_real Package
      2. A.4.2. The math_complex Package
    5. A.5. The std_logic_1164 Multivalue Logic System Package
    6. A.6. Standard Integer Numeric Packages
      1. A.6.1. The numeric_bit Package
      2. A.6.2. The numeric_std Package
      3. A.6.3. The numeric_bit_unsigned Package
      4. A.6.4. The numeric_std_unsigned Package
    7. A.7. Standard Fixed-Point Packages
      1. A.7.1. The fixed_float_types Package
      2. A.7.2. The fixed_generic_pkg Package
      3. A.7.3. The fixed_pkg Package
    8. A.8. Standard Floating-Point Packages
      1. A.8.1. The float_generic_pkg Package
      2. A.8.2. The float_pkg Package
  27. B. VHDL Syntax
    1. B.1. Design File
    2. B.2. Library Unit Declarations
    3. B.3. Declarations and Specifications
    4. B.4. Type Definitions
    5. B.5. Concurrent Statements
    6. B.6. Sequential Statements
    7. B.7. Interfaces and Associations
    8. B.8. Expressions and Names
  28. C. Answers to Exercises
    1. Chapter 1
    2. Chapter 2
    3. Chapter 3
    4. Chapter 4
    5. Chapter 5
    6. Chapter 6
    7. Chapter 7
    8. Chapter 8
    9. Chapter 9
    10. Chapter 10
    11. Chapter 11
    12. Chapter 12
    13. Chapter 13
    14. Chapter 14
    15. Chapter 15
    16. Chapter 16
    17. Chapter 17
    18. Chapter 18
    19. Chapter 19
    20. Chapter 20
    21. Chapter 21
    22. Chapter 22
    23. Chapter 23
  29. References