Exceptions
Publisher Summary
The Cortex-M3 provides a feature-packed exception architecture that supports a number of systems exceptions and external interrupts. This chapter provides definitions of Priority and explains different priority levels. It discusses how the Vector Table stores information about when the processor will need to locate the starting address of the exception handler. The behavior of interrupt inputs, pending behavior and several categories of faults are also reviewed. The exceptions useful for fault handling have also been reviewed and the concept of Supervisor Call (SVC) and Pendable Service Call (PendSV) have been discussed.
7.1 Exception Types
The Cortex™-M3 provides a feature-packed exception architecture that ...
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