APPENDIX C
Cortex-M3 Exceptions Quick Reference
C.1 Exception Types and Enables
Table C.1
Quick Summary of Cortex™-M3 Exception Types and Their Priority Configurations
| Exception Type | Name | Priority (Level Address) | Enable |
| 1 | Reset | –3 | Always |
| 2 | NMI | –2 | Always |
| 3 | Hard fault | –1 | Always |
| 4 | MemManage fault | Programmable (0xE000ED18) | NVIC SHCSR (0xE000ED24) bit[16] |
| 5 | Bus fault | Programmable (0xE000ED19) | NVIC SHCSR (0xE000ED24) bit[17] |
| 6 | Usage fault | Programmable (0xE000ED1A) | NVIC SHCSR (0xE000ED24) bit[18] |
| 7–10 | — | — | — |
| 11 | SVC | Programmable (0xE000ED1F) | Always |
| 12 | Debug monitor | Programmable (0xE000ED20) | NVIC DEMCR (0xE000EDFC) bit[16] |
| 13 | — | — | — |
| 14 | PendSV | Programmable (0xE000ED22) | Always |
| 15 | SYSTICK | Programmable (0xE000ED23) | SYSTICK CTRLSTAT (0xE000E010) ... |
Get The Definitive Guide to the ARM Cortex-M3, 2nd Edition now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
