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The Definitive Guide to the ARM Cortex-M3, 2nd Edition

Book Description

This user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap!

Whole chapters are dedicated to:
Debugging using the new CoreSight technology
Migrating effectively from the ARM7
The Memory Protection Unit
Interfaces, Exceptions,Interrupts
...and much more!

  • The only available guide to programming and using the groundbreaking ARM Cortex-M3 processor
  • Easy-to-understand examples, diagrams, quick reference appendices, full instruction and Thumb-2 instruction sets are included 
  • T teaches end users how to start from the ground up with the M3, and how to migrate from the ARM7

Table of Contents

  1. Cover image
  2. Table of Contents
  3. Copyright
  4. Foreword
  5. Foreword
  6. Preface
  7. Conventions
  8. Terms and Abbreviations
  9. CHAPTER 1. Introduction
  10. 1.1. What Is the ARM Cortex-M3 Processor?
  11. 1.2. Background of ARM and ARM Architecture
  12. 1.3. Instruction Set Development
  13. 1.4. The Thumb-2 Technology and Instruction Set Architecture
  14. 1.5. Cortex-M3 Processor Applications
  15. 1.6. Organization of This Book
  16. 1.7. Further Reading
  17. CHAPTER 2. Overview of the Cortex-M3
  18. 2.1. Fundamentals
  19. 2.2. Registers
  20. 2.3. Operation Modes
  21. 2.4. The Built-In Nested Vectored Interrupt Controller
  22. 2.5. The Memory Map
  23. 2.6. The Bus Interface
  24. 2.7. The MPU
  25. 2.8. The Instruction Set
  26. 2.9. Interrupts and Exceptions
  27. 2.10. Debugging Support
  28. 2.11. Characteristics Summary
  29. CHAPTER 3. Cortex-M3 Basics
  30. 3.1. Registers
  31. 3.2. Special Registers
  32. 3.3. Operation Mode
  33. 3.4. Exceptions and Interrupts
  34. 3.5. Vector Tables
  35. 3.6. Stack Memory Operations
  36. 3.7. Reset Sequence
  37. CHAPTER 4. Instruction Sets
  38. 4.1. Assembly Basics
  39. 4.2. Instruction List
  40. 4.3. Instruction Descriptions
  41. 4.4. Several Useful Instructions In the Cortex-M3
  42. CHAPTER 5. Memory Systems
  43. 5.1. Memory System Features Overview
  44. 5.2. Memory Maps
  45. 5.3. Memory Access Attributes
  46. 5.4. Default Memory Access Permissions
  47. 5.5. Bit-Band Operations
  48. 5.6. Unaligned Transfers
  49. 5.7. Exclusive Accesses
  50. 5.8. Endian Mode
  51. CHAPTER 6. Cortex-M3 Implementation Overview
  52. 6.1. The Pipeline
  53. 6.2. A Detailed Block Diagram
  54. 6.3. Bus Interfaces on the Cortex-M3
  55. 6.4. Other Interfaces on the Cortex-M3
  56. 6.5. The External PPB
  57. 6.6. Typical Connections
  58. 6.7. Reset Types and Reset Signals
  59. CHAPTER 7. Exceptions
  60. 7.1. Exception Types
  61. 7.2. Definitions of Priority
  62. 7.3. Vector Tables
  63. 7.4. Interrupt Inputs and Pending Behavior
  64. 7.5. Fault Exceptions
  65. 7.6. Supervisor Call and Pendable Service Call
  66. CHAPTER 8. The Nested Vectored Interrupt Controller and Interrupt Control
  67. 8.1. Nested Vectored Interrupt Controller Overview
  68. 8.2. The Basic Interrupt Configuration
  69. 8.3. Example Procedures In Setting Up an Interrupt
  70. 8.4. Software Interrupts
  71. 8.5. The SYSTICK Timer
  72. CHAPTER 9. Interrupt Behavior
  73. 9.1. Interrupt/Exception Sequences
  74. 9.2. Exception Exits
  75. 9.3. Nested Interrupts
  76. 9.4. Tail-Chaining Interrupts
  77. 9.5. Late Arrivals
  78. 9.6. More on the Exception Return Value
  79. 9.7. Interrupt Latency
  80. 9.8. Faults Related to Interrupts
  81. CHAPTER 10. Cortex-M3 Programming
  82. 10.1. Overview
  83. 10.2. A Typical Development Flow
  84. 10.3. Using C
  85. 10.4. CMSIS
  86. 10.5. Using Assembly
  87. 10.6. Using Exclusive Access for Semaphores
  88. 10.7. Using Bit Band for Semaphores
  89. 10.8. Working with Bit Field Extract and Table Branch
  90. CHAPTER 11. Exception Programming
  91. 11.1. Using Interrupts
  92. 11.2. Exception/Interrupt Handlers
  93. 11.3. Software Interrupts
  94. 11.4. Example of Vector Table Relocation
  95. 11.5. Using SVC
  96. 11.6. SVC Example: Use for Text Message Output Functions
  97. 11.7. Using SVC with C
  98. CHAPTER 12. Advanced Programming Features and System Behavior
  99. 12.1. Running a System with Two Separate Stacks
  100. 12.2. Double-Word Stack Alignment
  101. 12.3. Nonbase Thread Enable
  102. 12.4. Performance Considerations
  103. 12.5. Lockup Situations
  104. 12.6. FAULTMASK
  105. CHAPTER 13. The Memory Protection Unit
  106. 13.1. Overview
  107. 13.2. MPU Registers
  108. 13.3. Setting Up the MPU
  109. 13.4. Typical Setup
  110. CHAPTER 14. Other Cortex-M3 Features
  111. 14.1. The Systick Timer
  112. 14.2. Power Management
  113. 14.3. Multiprocessor Communication
  114. 14.4. Self-Reset Control
  115. CHAPTER 15. Debug Architecture
  116. 15.1. Debugging Features Overview
  117. 15.2. Coresight Overview
  118. 15.3. Debug Modes
  119. 15.4. Debugging Events
  120. 15.5. Breakpoint in the Cortex-M3
  121. 15.6. Accessing Register Content in Debug
  122. 15.7. Other Core Debugging Features
  123. CHAPTER 16. Debugging Components
  124. 16.1. Introduction
  125. 16.2. Trace Components: DWT
  126. 16.3. Trace Components: ITM
  127. 16.4. Trace Components: ETM
  128. 16.5. Trace Components: TPIU
  129. 16.6. The Flash Patch and Breakpoint Unit
  130. 16.7. The Advanced High-Performance Bus Access Port
  131. 16.8. ROM Table
  132. CHAPTER 17. Getting Started with the Cortex-M3 Processor
  133. 17.1. Choosing a Cortex-M3 Product
  134. 17.2. Development Tools
  135. 17.3. Differences between the Cortex-M3 Revision 0 and Revision 1
  136. 17.4. Differences between the Cortex-M3 Revision 1 and Revision 2
  137. 17.5. Benefits and Effects of the Revision 2 New Features
  138. 17.6. Differences between the Cortex-M3 and Cortex-M0
  139. CHAPTER 18. Porting Applications from the ARM7 to the Cortex-M3
  140. 18.1. Overview
  141. 18.2. System Characteristics
  142. 18.3. Assembly Language Files
  143. 18.4. C Program Files
  144. 18.5. Precompiled Object Files
  145. 18.6. Optimization
  146. CHAPTER 19. Starting Cortex-M3 Development Using the GNU Tool Chain
  147. 19.1. Background
  148. 19.2. Getting the GNU Tool Chain
  149. 19.3. Development Flow
  150. 19.4. Examples
  151. 19.5. Accessing Special Registers
  152. 19.6. Using Unsupported Instructions
  153. 19.7. Inline Assembler in the GNU C Compiler
  154. CHAPTER 20. Getting Started with the Keil RealView Microcontroller Development Kit
  155. 20.1. Overview
  156. 20.2. Getting Started with μVision
  157. 20.3. Outputting the “Hello World” Message Via Universal Asynchronous Receiver/Transmitter
  158. 20.4. Testing the Software
  159. 20.5. Using the Debugger
  160. 20.6. The Instruction Set Simulator
  161. 20.7. Modifying the Vector Table
  162. 20.8. Stopwatch Example with Interrupts with CMSIS
  163. 20.9. Porting Existing Applications to Use CMSIS
  164. CHAPTER 21. Programming the Cortex-M3 Microcontrollers in NI LabVIEW
  165. 21.1. Overview
  166. 21.2. What Is LabVIEW
  167. 21.3. Development Flow
  168. 21.4. Example of a LabVIEW Project
  169. 21.5. How It Works
  170. 21.6. Additional Features in LabVIEW
  171. 21.7. Porting to Another ARM Processor
  172. APPENDIX A. The Cortex-M3 Instruction Set, Reference Material
  173. APPENDIX B. The 16-Bit Thumb Instructions and Architecture Versions
  174. APPENDIX C. Cortex-M3 Exceptions Quick Reference
  175. APPENDIX D. Nested Vectored Interrupt Controller and System Control Block Registers Quick Reference
  176. APPENDIX E. Cortex-M3 Troubleshooting Guide
  177. APPENDIX F. Example Linker Script for CodeSourcery G++
  178. APPENDIX G. CMSIS Core Access Functions Reference
  179. APPENDIX H. Connectors for Debug and Tracers
  180. References
  181. Index