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The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition by Joseph Yiu

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Chapter 12

Memory Protection Unit

Abstract

This chapter introduces the Memory Protection Unit (MPU), an optional programmable unit in the Cortex®-M0+ processor, including its usages, the programmer's model, the configuration steps, and the differences between the MPU in ARMv6-M and ARMv7-M processors.

Keywords

Comparison of MPU with ARMv7-M architecture; Memory barrier; Memory protection unit (MPU) overview; MPU configuration; MPU registers; MPU usages; Sub-Region Disable

12.1. What is MPU?

The Memory Protection Unit (MPU) is a programmable block inside the processor that defines memory attributes (e.g., cacheable, bufferable, see Section 7.8) and memory access permissions. It is an optional feature for the Cortex®-M0+, Cortex-M3, Cortex-M4, and Cortex-M7 ...

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