The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition

Chapter 9

System Control and Low-Power Features

Abstract

This chapter introduces a group of memory-mapped registers inside the System Control Space of the Cortex^®-M0/Cortex-M0+ processors, including their usages like vector table relocation and self-reset. It then covers the low-power features of the Cortex-M0 and Cortex-M0+ processors such as sleep modes and the optional Wake-up Interrupt Controller.

Keywords

Registers in SCB; Self-reset; Send-event-on-pend; Sleep mode; Sleep-on-exit; System control block (SCB); Vector table relocation; Wake-up interrupt controller (WIC)

9.1. Brief Introduction of System Control Registers

Inside the System Control Space (SCS) address range (0xE000E000 to 0xE000EFFF), there are a number of control registers built-in ...