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The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition

Book Description

The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM’s Cortex-M0 and Cortex-M0+ processors and their programming techniques.

Written by ARM’s Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program code and software porting.

This new edition includes the differences between the Cortex-M0 and Cortex-M0+ processors such as architectural features (e.g. unprivileged execution level, vector table relocation), new chapters on low power designs and the Memory Protection Unit (MPU), the benefits of the Cortex-M0+ processor, such as the new single cycle I/O interface, higher energy efficiency, better performance and the Micro Trace Buffer (MTB) feature, updated software development tools, updated Real Time Operating System examples using Keil™ RTX with CMSIS-RTOS APIs, examples of using various Cortex-M0 and Cortex-M0+ based microcontrollers, and much more.



  • Provides detailed information on ARM® Cortex®-M0 and Cortex-M0+ Processors, including their architectures, programming model, instruction set, and interrupt handling
  • Presents detailed information on the differences between the Cortex-M0 and Cortex-M0+ processors
  • Covers software development flow, including examples for various development tools in both C and assembly languages
  • Includes in-depth coverage of design approaches and considerations for developing ultra low power embedded systems, the benchmark for energy efficiency in microcontrollers, and examples of utilizing low power features in microcontrollers

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Dedication
  6. Foreword
  7. Preface
  8. Acknowledgment
  9. Terms and Abbreviations
  10. Conventions
  11. References
  12. Chapter 1. Introduction
    1. 1.1. Welcome to the World of Embedded Processors
    2. 1.2. Understanding Different Types of Processors
    3. 1.3. What Is Inside a Microcontroller
    4. 1.4. There is Something About ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>&#8230;…
    5. 1.5. Resources on Using ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Processors and ARM Microcontrollers Processors and ARM Microcontrollers
  13. Chapter 2. Technical Overview
    1. 2.1. What are the Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0 and Cortex-M0+ Processors?-M0 and Cortex-M0+ Processors?
    2. 2.2. Block Diagrams
    3. 2.3. Typical Systems
    4. 2.4. What Is ARMv6-M Architecture?
    5. 2.5. Software Portability Between Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M Processors-M Processors
    6. 2.6. The Advantages of the ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Cortex Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0 and Cortex-M0+ Processor-M0 and Cortex-M0+ Processor
    7. 2.7. Applications of the Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0 and Cortex-M0+ Processors-M0 and Cortex-M0+ Processors
    8. 2.8. Why Using a 32-Bit Processor for Microcontroller Applications?
  14. Chapter 3. Introduction to Embedded Software Development
    1. 3.1. Welcome to Embedded System Programming
    2. 3.2. Some Basic Concepts
    3. 3.3. Introduction to ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Cortex Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M Programming-M Programming
    4. 3.4. Software Development Flow
    5. 3.5. Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Microcontroller Software Interface Standard Microcontroller Software Interface Standard
    6. 3.6. Other Information on Software Development
  15. Chapter 4. Architecture
    1. 4.1. Overview of ARMv6-M Architecture
    2. 4.2. Programmer's Model
    3. 4.3. Memory System
    4. 4.4. Stack Memory Operations
    5. 4.5. Exceptions and Interrupts
    6. 4.6. Nested Vectored Interrupt Controller
    7. 4.7. System Control Block
    8. 4.8. Debug System
    9. 4.9. Program Image and Start-up Sequence
  16. Chapter 5. Instruction Set
    1. 5.1. What Is Instruction Set
    2. 5.2. Background of ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> and Thumb and Thumb<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Instruction Set Instruction Set
    3. 5.3. Assembly Basics
    4. 5.4. Instruction List
    5. 5.5. Pseudo Instructions
  17. Chapter 6. Instruction Usage Examples
    1. 6.1. Overview
    2. 6.2. Program Control
    3. 6.3. Data Accesses
    4. 6.4. Data Type Conversion
    5. 6.5. Data Processing
  18. Chapter 7. Memory System
    1. 7.1. Memory Systems in Microcontrollers
    2. 7.2. Bus Systems in the Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0 and Cortex-M0+ Processors-M0 and Cortex-M0+ Processors
    3. 7.3. Memory Map
    4. 7.4. Program Memory, Boot Loader, and Memory Remapping
    5. 7.5. Data Memory
    6. 7.6. Little Endian and Big Endian Support
    7. 7.7. Data Type
    8. 7.8. Memory Attributes and Memory Access Permission
    9. 7.9. Effect of Hardware Behavior to Programming
  19. Chapter 8. Exceptions and Interrupts
    1. 8.1. What are Exceptions and Interrupts?
    2. 8.2. Exception Types on the Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0 and Cortex-M0+ Processors-M0 and Cortex-M0+ Processors
    3. 8.3. Brief Overview of the NVIC
    4. 8.4. Definition of Exception Priority Levels
    5. 8.5. Vector Table
    6. 8.6. Exception Sequence Overview
    7. 8.7. EXC_RETURN
    8. 8.8. NVIC Control Registers for Interrupt Control
    9. 8.9. Exception Masking Register (PRIMASK)
    10. 8.10. Interrupt Inputs and Pending Behavior
    11. 8.11. Details of Exception Entry Sequence
    12. 8.12. Details of Exception Exit Sequence
    13. 8.13. Interrupt Latency
  20. Chapter 9. System Control and Low-Power Features
    1. 9.1. Brief Introduction of System Control Registers
    2. 9.2. Registers in the SCBs
    3. 9.3. Using the Self-Reset Feature
    4. 9.4. Using the Vector Table Relocation Feature
    5. 9.5. Low-Power Features
  21. Chapter 10. Operating System Support Features
    1. 10.1. Overview of OS Support Features
    2. 10.2. Introduction to Operating Systems in Embedded World
    3. 10.3. The SysTick Timer
    4. 10.4. Process Stack and PSP
    5. 10.5. SVCall Exception
    6. 10.6. PendSV
    7. 10.7. Advanced Topics: Using SVC and PendSV in Programming
    8. 10.8. Advanced Topics: Context Switching in Action
  22. Chapter 11. Fault Handling
    1. 11.1. Fault Exception Overview
    2. 11.2. What Can Cause a Fault?
    3. 11.3. Analyze a Fault
    4. 11.4. Accidental Switching to ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> State State
    5. 11.5. Error Handling in Real Applications
    6. 11.6. Error Handling During Software Development
    7. 11.7. Lockup
    8. 11.8. Preventing Lockup
    9. 11.9. Comparison with Fault Handling in ARMv7-M Architecture
  23. Chapter 12. Memory Protection Unit
    1. 12.1. What is MPU?
    2. 12.2. MPU Use Cases
    3. 12.3. Technical Introduction
    4. 12.4. MPU Registers
    5. 12.5. Setting Up the MPU
    6. 12.6. Memory Barrier and MPU Configuration
    7. 12.7. Using Sub-Region Disable
    8. 12.8. Considerations When Using MPU
    9. 12.9. Comparing with the MPU in the Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M3/M4/M7 Processors-M3/M4/M7 Processors
  24. Chapter 13. Debug Features
    1. 13.1. Software Development and Debug Features
    2. 13.2. Debug Interface
    3. 13.3. Debug Features Overview
    4. 13.4. Debug System
    5. 13.5. Halt Mode and Debug Events
    6. 13.6. Instruction Tracing Support Using the MTB
  25. Chapter 14. Getting Started with the Keil Microcontroller Development Kit
    1. 14.1. Introduction to Keil Microcontroller Development Kit
    2. 14.2. Typical Program Compilation Flow
    3. 14.3. Introduction of the Hardware
    4. 14.4. Getting Started with μVision<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> IDE IDE
    5. 14.5. Using the IDE and the Debugger
    6. 14.6. Under the Hood
    7. 14.7. Customizations of the Project Environment
    8. 14.8. Using the Simulator
    9. 14.9. Execution in SRAM
    10. 14.10. Using MTB for Instruction Trace
  26. Chapter 15. Getting Started with IAR Embedded Workbench for ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>
    1. 15.1. Overview of IAR Embedded Workbench for ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>
    2. 15.2. Typical Program Compilation Flow
    3. 15.3. Creating a Simple Blinky Project
    4. 15.4. Project Options
    5. 15.5. Using MTB Instruction Trace with IAR EWARM
    6. 15.6. Hints and Tips
  27. Chapter 16. Getting Started with gcc (GNU Compiler Collection)
    1. 16.1. About the GNU Compiler Collection Tool Chain
    2. 16.2. About the Examples in This Chapter
    3. 16.3. Typical Development Flow
    4. 16.4. Creating a Simple Blinky Project
    5. 16.5. Overview of the Command Line Options
    6. 16.6. Flash Programming
    7. 16.7. Using Keil<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> MDK-ARM&#8482; with GNU Tools for ARM MDK-ARM™ with GNU Tools for ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Embedded Processors Embedded Processors
    8. 16.8. Using CooCox CoIDE with GNU Tools for ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Embedded Processors Embedded Processors
  28. Chapter 17. Getting Started with mbed™
    1. 17.1. What is mbed™
    2. 17.2. How the mbed™ System Works
    3. 17.3. Advantages of mbed™
    4. 17.4. Setting Up Your FRDM-KL25Z Board and mbed™ Account
    5. 17.5. Creating a Blinky Program
    6. 17.6. Common Peripheral Objects Support
    7. 17.7. Using printf
    8. 17.8. Application Example—A Model Railway Controller
    9. 17.9. Interrupts
    10. 17.10. Hints and Tips
  29. Chapter 18. Programming Examples
    1. 18.1. Producing Output with Universal Asynchronous Receiver/Transmitter
    2. 18.2. Handling printf
    3. 18.3. Developing Your Own Input and Output Functions
    4. 18.4. Interrupt Programming Examples
    5. 18.5. Application Example—Another Controller for a Model Train
    6. 18.6. Different Versions of CMSIS-CORE
  30. Chapter 19. Ultralow-Power Designs
    1. 19.1. Examples of Using Low-Power Features
    2. 19.2. Requirements of Low-Power Designs
    3. 19.3. Where Does the Power Go?
    4. 19.4. Developing Low-Power Applications
    5. 19.5. Debug Considerations
    6. 19.6. Benchmarking of Low-Power Devices
    7. 19.7. Example of Using Low-Power Features on Freescale KL25Z
    8. 19.8. Example of Using Low-Power Feature on LPC1114
  31. Chapter 20. Programming with Embedded OS
    1. 20.1. Introduction
    2. 20.2. Overview of the RTX Kernel
    3. 20.3. Using RTX in an Application
    4. 20.4. Debugging an Application with RTX
    5. 20.5. Trouble Shooting
    6. 20.6. Other Hints and Tips
  32. Chapter 21. Mixed Language Projects (C/C++ with Assembly)
    1. 21.1. Use of Assembly in Project Developments
    2. 21.2. Recommended Practices in Assembly Programming and AAPCS
    3. 21.3. Overview of an Assembly Function
    4. 21.4. Inline Assembly
    5. 21.5. Embedded Assembler Feature (ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Tool Chain) Tool Chain)
    6. 21.6. Mixed Language Projects
    7. 21.7. Creating Assembly Projects in Keil<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> MDK-ARM MDK-ARM
    8. 21.8. Generic Assembly Code for Interrupt Control
    9. 21.9. Other Programming Techniques for Assembly Language
    10. 21.10. Accessing Special Instructions
  33. Chapter 22. Software Porting
    1. 22.1. Overview
    2. 22.2. Porting Software from 8-Bit/16-Bit Microcontrollers to ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Cortex Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M-M
    3. 22.3. Differences between ARM7TDMI™ and Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0/M0+ Processor-M0/M0+ Processor
    4. 22.4. Porting Software from ARM7TDMI™ to the Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0/Cortex-M0+ Processors-M0/Cortex-M0+ Processors
    5. 22.5. Differences between Various Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M Processors-M Processors
    6. 22.6. General Software Modifications when Porting between Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M Processors-M Processors
    7. 22.7. Porting Software between Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0/M0+ and Cortex-M1-M0/M0+ and Cortex-M1
    8. 22.8. Porting Software between Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0/M0+ and Cortex-M3-M0/M0+ and Cortex-M3
    9. 22.9. Porting Software between Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0/M0+ and the Cortex-M4/M7 Processor-M0/M0+ and the Cortex-M4/M7 Processor
  34. Chapter 23. Advanced Topics
    1. 23.1. Bit Data Handling in C Programming
    2. 23.2. Startup Code in C
    3. 23.3. Stack Overflow Detection
    4. 23.4. Reentrant Interrupt Service Routine
    5. 23.5. Semaphore Implementation
    6. 23.6. Memory Ordering and Memory Barriers
  35. Appendix A. Instruction Set Quick Reference
  36. Appendix B. Exception Type Quick Reference
  37. Appendix C. CMSIS-CORE Quick Reference
  38. Appendix D. NVIC, SCB, and SysTick Registers Quick Reference
  39. Appendix E. Debug Registers Quick Reference
  40. Appendix F. Debug Connector Arrangements
  41. Appendix G. Trouble Shooting
  42. Appendix H. A Breadboard Project with an ARM<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup> Cortex Cortex<sup xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">&#174;</sup>-M0 Microcontroller-M0 Microcontroller
  43. Index