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System-on-Chip Test Architectures: Nanometer Design for Testability

Book Description

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Table of Contents

  1. Copyright
  2. The Morgan Kaufmann Series in Systems on Silicon
  3. Preface
  4. In the Classroom
  5. Acknowledgments
  6. Contributors
  7. About the Editors
  8. 1. Introduction
    1. About This Chapter
    2. 1.1. Importance of System-on-Chip Testing
      1. 1.1.1. Yield and Reject Rate
        1. Example 1.1
      2. 1.1.2. Reliability and System Availability
        1. Example 1.2
    3. 1.2. Basics of SOC Testing
      1. 1.2.1. Boundary Scan (IEEE 1149.1 Standard)
      2. 1.2.2. Boundary Scan Extension (IEEE 1149.6 Standard)
      3. 1.2.3. Boundary-Scan Accessible Embedded Instruments (IEEE P1687)
      4. 1.2.4. Core-Based Testing (IEEE 1500 Standard)
      5. 1.2.5. Analog Boundary Scan (IEEE 1149.4 Standard)
    4. 1.3. Basics of Memory Testing
    5. 1.4. SOC Design Examples
      1. 1.4.1. BioMEMS Sensor
      2. 1.4.2. Network-on-Chip Processor
    6. 1.5. About This Book
      1. 1.5.1. DFT Architectures
      2. 1.5.2. New Fault Models and Advanced Techniques
      3. 1.5.3. Yield and Reliability Enhancement
      4. 1.5.4. Nanotechnology Testing Aspects
    7. 1.6. Exercises
    8. Acknowledgments
    9. References
      1. R1.0. Books
      2. R1.1. Importance of System-on-Chip Testing
      3. R1.2. Basics of SOC Testing
      4. R1.3. Basics of Memory Testing
      5. R1.4. SOC Design Examples
      6. R1.5. About This Book
  9. 2. Digital Test Architectures
    1. About This Chapter
    2. 2.1. Introduction
    3. 2.2. Scan Design
      1. 2.2.1. Scan Architectures
        1. 2.2.1.1. Muxed-D Scan Design
        2. 2.2.1.2. Clocked-Scan Design
        3. 2.2.1.3. LSSD Scan Design
        4. 2.2.1.4. Enhanced-Scan Design
      2. 2.2.2. Low-Power Scan Architectures
        1. 2.2.2.1. Reduced-Voltage Low-Power Scan Design
        2. 2.2.2.2. Reduced-Frequency Low-Power Scan Design
        3. 2.2.2.3. Multi-Phase or Multi-Duty Low-Power Scan Design
        4. 2.2.2.4. Bandwidth-Matching Low-Power Scan Design
        5. 2.2.2.5. Hybrid Low-Power Scan Design
      3. 2.2.3. At-Speed Scan Architectures
    4. 2.3. Logic Built-In Self-Test
      1. 2.3.1. Logic BIST Architectures
        1. 2.3.1.1. Self-Testing Using MISR and Parallel SRSG (STUMPS)
        2. 2.3.1.2. Concurrent Built-In Logic Block Observer (CBILBO)
      2. 2.3.2. Coverage-Driven Logic BIST Architectures
        1. 2.3.2.1. Weighted Pattern Generation
        2. 2.3.2.2. Test Point Insertion
          1. Test Point Placement
          2. Control Point Activation
        3. 2.3.2.3. Mixed-Mode BIST
          1. ROM Compression
          2. LFSR Reseeding
          3. Embedding Deterministic Patterns
        4. 2.3.2.4. Hybrid BIST
      3. 2.3.3. Low-Power Logic BIST Architectures
        1. 2.3.3.1. Low-Transition BIST Design
        2. 2.3.3.2. Test-Vector-Inhibiting BIST Design
        3. 2.3.3.3. Modified LFSR Low-Power BIST Design
      4. 2.3.4. At-Speed Logic BIST Architectures
        1. 2.3.4.1. Single-Capture
          1. One-Hot Single-Capture
          2. Staggered Single-Capture
        2. 2.3.4.2. Skewed-Load
          1. One-Hot Skewed-Load
          2. Aligned Skewed-Load
          3. Staggered Skewed-Load
        3. 2.3.4.3. Double-Capture
          1. One-Hot Double-Capture
          2. Aligned Double-Capture
          3. Staggered Double-Capture
      5. 2.3.5. Industry Practices
    5. 2.4. Test Compression
      1. 2.4.1. Circuits for Test Stimulus Compression
        1. 2.4.1.1. Linear-Decompression-Based Schemes
          1. Combinational Linear Decompressors
          2. Sequential Linear Decompressors
        2. 2.4.1.2. Broadcast-Scan-Based Schemes
          1. Broadcast Scan
          2. Illinois Scan
          3. Multiple-Input Broadcast Scan
          4. Reconfigurable Broadcast Scan
          5. Virtual Scan
        3. 2.4.1.3. Comparison
      2. 2.4.2. Circuits for Test Response Compaction
        1. 2.4.2.1. Space Compaction
          1. X-Compact
          2. Theorem 2.1
          3. Theorem 2.2
          4. X-Blocking
          5. X-Masking
          6. X-Impact
          7. Example 2.1
          8. Example 2.2
        2. 2.4.2.2. Time Compaction
        3. 2.4.2.3. Mixed Time and Space Compaction
          1. Example 2.3
      3. 2.4.3. Low-Power Test Compression Architectures
      4. 2.4.4. Industry Practices
    6. 2.5. Random-Access Scan Design
      1. 2.5.1. Random-Access Scan Architectures
        1. 2.5.1.1. Progressive Random-Access Scan Design
        2. 2.5.1.2. Shift-Addressable Random-Access Scan Design
      2. 2.5.2. Test Compression RAS Architectures
      3. 2.5.3. At-Speed RAS Architectures
    7. 2.6. Concluding Remarks
    8. 2.7. Exercises
    9. Acknowledgments
    10. References
      1. R2.0. Books
      2. R2.1. Introduction
      3. R2.2. Scan Design
      4. R2.3. Logic Built-In Self-Test
      5. R2.4. Test Compression
      6. R2.5. Random-Access Scan Design
      7. R2.6. Concluding Remarks
  10. 3. Fault-Tolerant Design
    1. About This Chapter
    2. 3.1. Introduction
    3. 3.2. Fundamentals of Fault Tolerance
      1. 3.2.1. Reliability
      2. 3.2.2. Mean Time to Failure (MTTF)
        1. Example 3.1
        2. Example 3.2
      3. 3.2.3. Maintainability
      4. 3.2.4. Availability
        1. Example 3.3
    4. 3.3. Fundamentals of Coding Theory
      1. 3.3.1. Linear Block Codes
        1. Example 3.4
        2. Example 3.5
        3. Example 3.6
        4. Example 3.7
        5. Example 3.8
        6. Example 3.9
        7. Example 3.10
        8. Example 3.11
        9. Example 3.12
      2. 3.3.2. Unidirectional Codes
        1. 3.3.2.1. Two-Rail Codes
        2. 3.3.2.2. Berger Codes
          1. Example 3.13
        3. 3.3.2.3. Constant Weight Codes
          1. Example 3.14
      3. 3.3.3. Cyclic Codes
        1. Example 3.15
        2. Example 3.16
        3. Example 3.17
        4. Example 3.18
        5. Example 3.19
    5. 3.4. Fault Tolerance Schemes
      1. 3.4.1. Hardware Redundancy
        1. 3.4.1.1. Static Redundancy
          1. Triple Modular Redundancy (TMR)
          2. Example 3.20
          3. N-Modular Redundancy (NMR)
          4. Interwoven Logic
        2. 3.4.1.2. Dynamic Redundancy
          1. Unpowered (Cold) Spares
          2. Powered (Hot) Spares
          3. TMR/Simplex
        3. 3.4.1.3. Hybrid Redundancy
          1. TMR with Spares
          2. Self-Purging Redundancy
      2. 3.4.2. Time Redundancy
        1. 3.4.2.1. Repeated Execution
        2. 3.4.2.2. Multiple Sampling of Outputs
        3. 3.4.2.3. Diverse Recomputation
      3. 3.4.3. Information Redundancy
        1. 3.4.3.1. Error Detection
          1. Duplicate-and-Compare
          2. Single-Bit Parity Code
          3. Parity-Check Codes
          4. Berger Codes
          5. Constant Weight Codes
        2. 3.4.3.2. Error Correction
    6. 3.5. Industry Practices
    7. 3.6. Concluding Remarks
    8. 3.7. Exercises
    9. Acknowledgments
    10. References
      1. R3.0. Books
      2. R3.2. Fundamentals of Fault Tolerance
      3. R3.3. Fundamentals of Coding Theory
      4. R3.4. Fault Tolerance Schemes
  11. 4. System/Network-on-Chip Test Architectures
    1. About This Chapter
    2. 4.1. Introduction
    3. 4.2. System-on-Chip (SOC) Testing
      1. 4.2.1. Modular Testing of SOCs
      2. 4.2.2. Wrapper Design and Optimization
      3. 4.2.3. TAM Design and Optimization
      4. 4.2.4. Test Scheduling
        1. Integrated TAM Optimization and Test Scheduling
      5. 4.2.5. Modular Testing of Mixed-Signal SOCs
        1. Analog Test Wrapper Modes
      6. 4.2.6. Modular Testing of Hierarchical SOCs
      7. 4.2.7. Wafer-Sort Optimization for Core-Based SOCs
    4. 4.3. Network-on-Chip (NOC) Testing
      1. 4.3.1. NOC Architectures
      2. 4.3.2. Testing of Embedded Cores
        1. 4.3.2.1. Reuse of On-Chip Network for Testing
        2. 4.3.2.2. Test Scheduling
        3. 4.3.2.3. Test Access Methods and Test Interface
        4. 4.3.2.4. Efficient Reuse of Network
        5. 4.3.2.5. Power-Aware and Thermal-Aware Testing
      3. 4.3.3. Testing of On-Chip Networks
        1. 4.3.3.1. Testing of Interconnect Infrastructures
        2. 4.3.3.2. Testing of Routers
        3. 4.3.3.3. Testing of Network Interfaces and Integrated System Testing
    5. 4.4. Design and Test Practice: Case Studies
      1. 4.4.1. SOC Testing for PNX8550 System Chip
      2. 4.4.2. NOC Testing for a High-End TV System
    6. 4.5. Concluding Remarks
    7. 4.6. Exercises
    8. Acknowledgments
    9. References
      1. R4.0. Books
      2. R4.1. Introduction
      3. R4.2. System-on-Chip (SOC) Testing
      4. R4.3. Network-on-Chip (NOC) Testing
      5. R4.4. Design and Test Practice: Case Studies
      6. R4.5. Concluding Remarks
  12. 5. SIP Test Architectures
    1. About This Chapter
    2. 5.1. Introduction
      1. 5.1.1. SIP Definition
      2. 5.1.2. SIP Examples
      3. 5.1.3. Yield and Quality Challenges
      4. 5.1.4. Test Strategy
    3. 5.2. Bare Die Test
      1. 5.2.1. Mechanical Probing Techniques
      2. 5.2.2. Electrical Probing Techniques
      3. 5.2.3. Reliability Screens
    4. 5.3. Functional System Test
      1. 5.3.1. Path-Based Testing
      2. 5.3.2. Loopback Techniques: DFT and DSP
    5. 5.4. Test of Embedded Components
      1. 5.4.1. SIP Test Access Port
      2. 5.4.2. Interconnections
      3. 5.4.3. Digital and Memory Dies
      4. 5.4.4. Analog and RF Components
        1. 5.4.4.1. Test Equipment Issues
        2. 5.4.4.2. Test of Analog, Mixed-Signal, and RF Dies
      5. 5.4.5. MEMS
    6. 5.5. Concluding Remarks
    7. 5.6. Exercises
    8. Acknowledgments
    9. References
      1. R5.0. Books
      2. R5.1. Introduction
      3. R5.2. Bare Die Test
      4. R5.3. Functional System Test
      5. R5.4. Test of Embedded Components
  13. 6. Delay Testing
    1. About This Chapter
    2. 6.1. Introduction
    3. 6.2. Delay Test Application
      1. 6.2.1. Enhanced Scan
      2. 6.2.2. Muxed-D Scan
      3. 6.2.3. Scan Clocking
      4. 6.2.4. Faster-Than-At-Speed Testing
    4. 6.3. Delay Fault Models
      1. 6.3.1. Transition Fault Model
      2. 6.3.2. Inline-Delay Fault Model
      3. 6.3.3. Gate-Delay Fault Model
      4. 6.3.4. Path-Delay Fault Model
      5. 6.3.5. Defect-Based Delay Fault Models
    5. 6.4. Delay Test Sensitization
    6. 6.5. Delay Fault Simulation
      1. 6.5.1. Transition Fault Simulation
      2. 6.5.2. Gate/Line Delay Fault Simulation
      3. 6.5.3. Path-Delay Fault Simulation
      4. 6.5.4. Defect-Based Delay Fault Model Simulation
    7. 6.6. Delay Fault Test Generation
      1. 6.6.1. Transition/Inline Fault ATPG
      2. 6.6.2. Gate-Delay Fault ATPG
      3. 6.6.3. Path-Delay Fault ATPG
      4. 6.6.4. K Longest Paths per Gate (KLPG) ATPG
    8. 6.7. Pseudo-Functional Testing to Avoid Over-Testing
      1. 6.7.1. Computing Constraints
        1. 6.7.1.1. Pair-Wise Constraints
        2. 6.7.1.2. Multiliteral Constraints
      2. 6.7.2. Constrained ATPG
    9. 6.8. Concluding Remarks
    10. 6.9. Exercises
    11. Acknowledgments
    12. References
      1. R6.0. Books
      2. R6.2. Delay Test Application
      3. R6.3. Delay Fault Models
      4. R6.4. Delay Test Sensitization
      5. R6.5. Delay Fault Simulation
      6. R6.6. Delay Fault Test Generation
      7. R6.7. Pseudo-Functional Testing to Avoid Over-Testing
  14. 7. Low-Power Testing
    1. About This Chapter
    2. 7.1. Introduction
    3. 7.2. Energy and Power Modeling
      1. 7.2.1. Basics of Circuit Theory
      2. 7.2.2. Terminology
      3. 7.2.3. Test-Power Modeling and Evaluation
    4. 7.3. Test Power Issues
      1. 7.3.1. Thermal Effects
      2. 7.3.2. Noise Phenomena
      3. 7.3.3. Miscellaneous Issues
    5. 7.4. Low-Power Scan Testing
      1. 7.4.1. Basics of Scan Testing
      2. 7.4.2. ATPG and X-Filling Techniques
      3. 7.4.3. Low-Power Test Vector Compaction
      4. 7.4.4. Shift Control Techniques
      5. 7.4.5. Scan Cell Ordering
      6. 7.4.6. Scan Architecture Modification
      7. 7.4.7. Scan Clock Splitting
    6. 7.5. Low-Power Built-In Self-Test
      1. 7.5.1. Basics of Logic BIST
      2. 7.5.2. LFSR Tuning
      3. 7.5.3. Low-Power Test Pattern Generators
      4. 7.5.4. Vector Filtering BIST
      5. 7.5.5. Circuit Partitioning
      6. 7.5.6. Power-Aware Test Scheduling
    7. 7.6. Low-Power Test Data Compression
      1. 7.6.1. Coding-Based Schemes
      2. 7.6.2. Linear-Decompression-Based Schemes
      3. 7.6.3. Broadcast-Scan-Based Schemes
    8. 7.7. Low-Power RAM Testing
    9. 7.8. Concluding Remarks
    10. 7.9. Exercises
    11. Acknowledgments
    12. References
      1. R7.0. Books
      2. R7.1. Introduction
      3. R7.2. Energy and Power Modeling
      4. R7.3. Test Power Issues
      5. R7.4. Low-Power Scan Testing
      6. R7.5. Low-Power Built-In Self-Test
      7. R7.6. Low-Power Test Data Compression
      8. R7.7. Low-Power RAM Testing
      9. R7.8. Concluding Remarks
  15. 8. Coping with Physical Failures, Soft Errors, and Reliability Issues
    1. About This Chapter
    2. 8.1. Introduction
    3. 8.2. Signal Integrity
      1. 8.2.1. Basic Concept of Integrity Loss
      2. 8.2.2. Sources of Integrity Loss
        1. 8.2.2.1. Interconnects
        2. 8.2.2.2. Power Supply Noise
        3. 8.2.2.3. Process Variations
      3. 8.2.3. Integrity Loss Sensors/Monitors
        1. 8.2.3.1. Current Sensor
        2. 8.2.3.2. Power Supply Noise Monitor
        3. 8.2.3.3. Noise Detector (ND) Sensor
        4. 8.2.3.4. Integrity Loss Sensor (ILS)
        5. 8.2.3.5. Jitter Monitor
        6. 8.2.3.6. Process Variation Sensor
      4. 8.2.4. Readout Architectures
        1. 8.2.4.1. BIST-Based Architecture
        2. 8.2.4.2. Scan-Based Architecture
        3. 8.2.4.3. PV-Test Architecture
    4. 8.3. Manufacturing Defects, Process Variations, and Reliability
      1. 8.3.1. Fault Detection
        1. 8.3.1.1. Structural Tests
        2. 8.3.1.2. Defect-Based Tests
          1. Small Delay Defect Tests
          2. Bridging Defect Tests
          3. N-Detect Tests
          4. IDDQTests
          5. MinVDDTests
          6. VLV Tests
        3. 8.3.1.3. Functional Tests
      2. 8.3.2. Reliability Stress
      3. 8.3.3. Redundancy and Memory Repair
      4. 8.3.4. Process Sensors and Adaptive Design
        1. 8.3.4.1. Process Variation Sensor
        2. 8.3.4.2. Thermal Sensor
        3. 8.3.4.3. Dynamic Voltage Scaling
    5. 8.4. Soft Errors
      1. 8.4.1. Sources of Soft Errors and SER Trends
      2. 8.4.2. Coping with Soft Errors
        1. 8.4.2.1. Fault Tolerance
        2. 8.4.2.2. Error-Resilient Microarchitectures
          1. DIVA
          2. Razor
        3. 8.4.2.3. Soft Error Mitigation
          1. Built-In Soft-Error Resilience
          2. Circuit-Level Approaches
    6. 8.5. Defect and Error Tolerance
      1. 8.5.1. Defect Tolerance
      2. 8.5.2. Error Tolerance
    7. 8.6. Concluding Remarks
    8. 8.7. Exercises
    9. Acknowledgments
    10. References
      1. R8.0. Books
      2. R8.1. Introduction
      3. R8.2. Signal Integrity
      4. R8.3. Manufacturing Defects, Process Variations, and Reliability
      5. R8.4. Soft Errors
      6. R8.5. Defect and Error Tolerance
      7. R8.6. Concluding Remarks
  16. 9. Design for Manufacturability and Yield
    1. About This Chapter
    2. 9.1. Introduction
    3. 9.2. Yield
    4. 9.3. Components of Yield
      1. 9.3.1. Yield Models
      2. 9.3.2. Yield and Repair
    5. 9.4. Photolithography
    6. 9.5. DFM and DFY
      1. 9.5.1. Photolithography
      2. 9.5.2. Critical Area
      3. 9.5.3. Yield Variation over Time
      4. 9.5.4. DFT and DFM/DFY
    7. 9.6. Variability
      1. 9.6.1. Sources of Variability
      2. 9.6.2. Deterministic versus Random Variability
      3. 9.6.3. Variability versus Defectivity
      4. 9.6.4. Putting It All Together
    8. 9.7. Metrics for DFX
      1. 9.7.1. The Ideal Case
        1. Observation 1
        2. Observation 2
      2. 9.7.2. Potential DFY Metrics
        1. 9.7.2.1. Critical Area
        2. 9.7.2.2. RET-Based Metrics
        3. 9.7.2.3. Example DRC-Based Metrics for DFM
    9. 9.8. Concluding Remarks
    10. 9.9. Exercises
    11. Acknowledgments
    12. References
      1. R9.0. Books
      2. R9.1. Introduction
      3. R9.2. Yield
      4. R9.3. Components of Yield
      5. R9.4. Photolithography
      6. R9.5. DFM and DFY
      7. R9.6. Variability
      8. R9.7. Metrics for DFX
      9. R9.8. Concluding Remarks
  17. 10. Design for Debug and Diagnosis
    1. About This Chapter
    2. 10.1. Introduction
      1. 10.1.1. What Are Debug and Diagnosis?
      2. 10.1.2. Where Is Diagnosis Used?
      3. 10.1.3. IC-Level Debug and Diagnosis
      4. 10.1.4. Silicon Debug versus Defect Diagnosis
      5. 10.1.5. Design for Debug and Diagnosis
    3. 10.2. Logic Design for Debug and Diagnosis (DFD) Structures
      1. 10.2.1. Scan
      2. 10.2.2. Observation-Only Scan
      3. 10.2.3. Observation Points with Multiplexers
      4. 10.2.4. Array Dump and Trace Logic Analyzer
      5. 10.2.5. Clock Control
      6. 10.2.6. Partitioning, Isolation, and De-featuring
      7. 10.2.7. Reconfigurable Logic
    4. 10.3. Probing Technologies
      1. 10.3.1. Mechanical Probing
      2. 10.3.2. Injection-Based Probing
        1. 10.3.2.1. E-beam Probing
        2. 10.3.2.2. Laser Voltage Probing
      3. 10.3.3. Emission-Based Probing
        1. 10.3.3.1. Infrared Emission Microscopy (IREM)
        2. 10.3.3.2. Picosecond Imaging Circuit Analysis (PICA)
        3. 10.3.3.3. Time Resolved Emissions (TRE)
    5. 10.4. Circuit Editing
      1. 10.4.1. Focused Ion Beam
      2. 10.4.2. Layout-Database-Driven Navigation System
      3. 10.4.3. Spare Gates and Spare Wires
    6. 10.5. Physical DFD Structures
      1. 10.5.1. Physical DFD for Pico-Probing
      2. 10.5.2. Physical DFD for E-Beam
      3. 10.5.3. Physical DFD for FIB and Probing
    7. 10.6. Diagnosis and Debug Process
      1. 10.6.1. Diagnosis Techniques and Strategies
      2. 10.6.2. Silicon Debug Process and Flow
      3. 10.6.3. Debug Techniques and Methodology
    8. 10.7. Concluding Remarks
    9. 10.8. Exercises
    10. Acknowledgments
    11. References
      1. R10.0. Books
      2. R10.1. Introduction
      3. R10.2. Logic Design for Debug and Diagnosis (DFD) Structures
      4. R10.3. Probing Technologies
      5. R10.4. Circuit Editing
      6. R10.6. Diagnosis and Debug Process
      7. R10.7. Concluding Remarks
  18. 11. Software-Based Self-Testing
    1. About This Chapter
    2. 11.1. Introduction
    3. 11.2. Software-Based Self-Testing Paradigm
      1. 11.2.1. Self-Test Flow
      2. 11.2.2. Comparison with Structural BIST
    4. 11.3. Processor Functional Fault Self-Testing
      1. 11.3.1. Processor Model
      2. 11.3.2. Functional-Level Fault Models
      3. 11.3.3. Test Generation Procedures
        1. 11.3.3.1. Test Generation for Register Decoding Fault
        2. 11.3.3.2. Test Generation for Instruction Decoding and Control Fault
        3. 11.3.3.3. Test Generation for Data Transfer and Storage Function
        4. 11.3.3.4. Test Generation for Data Manipulation Function
        5. 11.3.3.5. Test Generation Complexity
    5. 11.4. Processor Structural Fault Self-Testing
      1. 11.4.1. Test Flow
        1. 11.4.1.1. Test Preparation
        2. 11.4.1.2. Self-Testing
      2. 11.4.2. Stuck-At Fault Testing
        1. 11.4.2.1. Instruction-Imposed I/O Constraint Extraction
        2. 11.4.2.2. Constrained Component Test Generation
        3. 11.4.2.3. Test Program Synthesis
        4. 11.4.2.4. Processor Self-Testing
      3. 11.4.3. Test Program Synthesis Using Virtual Constraint Circuits (VCCs)
      4. 11.4.4. Delay Fault Testing
        1. 11.4.4.1. Functionally Untestable Delay Faults
        2. 11.4.4.2. Constraint Extraction
        3. 11.4.4.3. Test Program Generation
      5. 11.4.5. Functional Random Instruction Testing
    6. 11.5. Processor Self-Diagnosis
      1. 11.5.1. Challenges to SBST-Based Processor Diagnosis
      2. 11.5.2. Diagnostic Test Program Generation
    7. 11.6. Testing Global Interconnect
      1. 11.6.1. Maximum Aggressor (MA) Fault Model
      2. 11.6.2. Processor-Based Address and Data Bus Testing
        1. 11.6.2.1. Data Bus Testing
        2. 11.6.2.2. Address Bus Testing
      3. 11.6.3. Processor-Based Functional MA Testing
    8. 11.7. Testing Nonprogrammable Cores
      1. 11.7.1. Preprocessing Phase
      2. 11.7.2. Core Test Phase
    9. 11.8. Instruction-Level DFT
      1. 11.8.1. Instruction-Level DFT Concept
      2. 11.8.2. Testability Instructions
      3. 11.8.3. Test Optimization Instructions
    10. 11.9. DSP-Based Analog/Mixed-Signal Component Testing
    11. 11.10. Concluding Remarks
    12. 11.11. Exercises
    13. Acknowledgments
    14. References
      1. R11.0. Books
      2. R11.1. Introduction
      3. R11.2. Software-Based Self-Testing Paradigm
      4. R11.3. Processor Functional Fault Self-Testing
      5. R11.4. Processor Structural Fault Self-Testing
      6. R11.5. Processor Self-Diagnosis
      7. R11.6. Testing Global Interconnect
      8. R11.7. Testing Nonprogrammable Cores
      9. R11.8. Instruction-Level DFT
      10. R11.9. DSP-Based Analog/Mixed-Signal Component Testing
  19. 12. Field Programmable Gate Array Testing
    1. About This Chapter
    2. 12.1. Overview of FPGAs
      1. 12.1.1. Architecture
      2. 12.1.2. Configuration
      3. 12.1.3. The Testing Problem
    3. 12.2. Testing Approaches
      1. 12.2.1. External Testing and Built-In Self-Test
      2. 12.2.2. Online and Offline Testing
      3. 12.2.3. Application Dependent and Independent Testing
    4. 12.3. BIST of Programmable Resources
      1. 12.3.1. Logic Resources
        1. 12.3.1.1. Programmable Logic Blocks
        2. 12.3.1.2. Input/Output Cells
        3. 12.3.1.3. Specialized Cores
        4. 12.3.1.4. Diagnosis
      2. 12.3.2. Interconnect Resources
    5. 12.4. Embedded Processor-Based Testing
    6. 12.5. Concluding Remarks
    7. 12.6. Exercises
    8. Acknowledgments
    9. References
      1. R12.0. Books
      2. R12.1. Overview of FPGAs
      3. R12.2. Testing Approaches
      4. R12.3. BIST of Programmable Resources
      5. R12.4. Embedded Processor-Based Testing
      6. R12.5. Concluding Remarks
  20. 13. MEMS Testing
    1. About This Chapter
    2. 13.1. Introduction
    3. 13.2. MEMS Testing Considerations
    4. 13.3. Test Methods and Instrumentation for MEMS
      1. 13.3.1. Electrical Test
      2. 13.3.2. Optical Test Methods
      3. 13.3.3. Material Property Measurements
      4. 13.3.4. Failure Modes and Analysis
      5. 13.3.5. Mechanical Test Methods
      6. 13.3.6. Environmental Testing
    5. 13.4. RF MEMS Devices
      1. 13.4.1. RF MEMS Switches
      2. 13.4.2. RF MEMS Resonators
    6. 13.5. Optical MEMS Devices
    7. 13.6. Fluidic MEMS Devices
      1. 13.6.1. MEMS Pressure Sensor
      2. 13.6.2. MEMS Humidity Sensor
    8. 13.7. Dynamic MEMS Devices
      1. 13.7.1. MEMS Microphone
      2. 13.7.2. MEMS Accelerometer
      3. 13.7.3. MEMS Gyroscope
    9. 13.8. Testing Digital Microfluidic Biochips
      1. 13.8.1. Overview of Digital Microfluidic Biochips
      2. 13.8.2. Fault Modeling
      3. 13.8.3. Test Techniques
      4. 13.8.4. Application to a Fabricated Biochip
    10. 13.9. DFT and BIST for MEMS
      1. 13.9.1. Overview of DFT and BIST Techniques
      2. 13.9.2. MEMS BIST Examples
    11. 13.10. Concluding Remarks
    12. 13.11. Exercises
    13. Acknowledgments
    14. References
      1. R13.0. Books
      2. R13.1. Introduction
      3. R13.2. MEMS Testing Considerations
      4. R13.3. Test Methods and Instrumentation for MEMS
      5. R13.4. RF MEMS Devices
      6. R13.5. Optical MEMS Devices
      7. R13.6. Fluidic MEMS Devices
      8. R13.7. Dynamic MEMS Devices
      9. R13.8. Testing Digital Microfluidic Biochips
      10. R13.9. DFT and BIST for MEMS
  21. 14. High-Speed I/O Interfaces
    1. About This Chapter
    2. 14.1. Introduction
    3. 14.2. High-Speed I/O Architectures
      1. 14.2.1. Global Clock I/O Architectures
      2. 14.2.2. Source Synchronous I/O Architectures
      3. 14.2.3. Embedded Clock I/O Architectures
        1. 14.2.3.1. Jitter Components
        2. 14.2.3.2. Jitter Separation
          1. Jitter Separation Based on Statistical PDF or CDF
          2. Jitter Separation Based on Frequency Spectrum
        3. 14.2.3.3. Jitter, Noise, and Bit-Error-Rate Interactions
          1. Receiver Jitter Transfer Function
          2. Receiver Jitter Tolerance Function
    4. 14.3. Testing of I/O Interfaces
      1. 14.3.1. Testing of Global Clock I/O
      2. 14.3.2. Testing of Source Synchronous I/O
      3. 14.3.3. Testing of Embedded Clock High-Speed Serial I/O
        1. 14.3.3.1. Transmitter
        2. 14.3.3.2. Channel or Medium
        3. 14.3.3.3. Receiver
        4. 14.3.3.4. Reference Clock
        5. 14.3.3.5. System-Level Bit-Error-Rate Estimation
        6. 14.3.3.6. Tester Apparatus Considerations
          1. Hardware Bandwidth and Accuracy
          2. “In Situ” Testing to Emulate the Receiver
          3. Throughput
    5. 14.4. DFT-Assisted Testing
      1. 14.4.1. AC Loopback Testing
      2. 14.4.2. High-Speed Serial-Link Loopback Testing
      3. 14.4.3. Testing the Equalizers
    6. 14.5. System-Level Interconnect Testing
      1. 14.5.1. Interconnect Testing with Boundary Scan
      2. 14.5.2. Interconnect Testing with High-Speed Boundary Scan
      3. 14.5.3. Interconnect Built-In Self-Test
    7. 14.6. Future Challenges
    8. 14.7. Concluding Remarks
    9. 14.8. Exercises
    10. Acknowledgments
    11. References
      1. R14.0. Books
      2. R14.1. Introduction
      3. R14.2. High-Speed I/O Architectures
      4. R14.3. Testing of I/O Interfaces
      5. R14.4. DFT-Assisted Testing
      6. R14.5. System-Level Interconnect Testing
      7. R14.6. Future Challenges
  22. 15. Analog and Mixed-Signal Test Architectures
    1. About This Chapter
    2. 15.1. Introduction
    3. 15.2. Analog Functional Testing
      1. 15.2.1. Frequency Response Testing
      2. 15.2.2. Linearity Testing
      3. 15.2.3. Signal-to-Noise Ratio Testing
      4. 15.2.4. Quantization Noise
      5. 15.2.5. Phase Noise
      6. 15.2.6. Noise in Phase-Locked Loops
        1. 15.2.6.1. In-Band PLL Phase Noise
        2. 15.2.6.2. Out-Band PLL Phase Noise
        3. 15.2.6.3. Optimal Loop Setting
      7. 15.2.7. DAC Nonlinearity Testing
    4. 15.3. Analog and Mixed-Signal Test Architectures
    5. 15.4. Defect-Oriented Mixed-Signal BIST Approaches
    6. 15.5. FFT-Based Mixed-Signal BIST
      1. 15.5.1. FFT
      2. 15.5.2. Inverse FFT
      3. 15.5.3. FFT-Based BIST Architecture
      4. 15.5.4. FFT-Based Output Response Analysis
      5. 15.5.5. FFT-Based Test Pattern Generation
    7. 15.6. Direct Digital Synthesis BIST
      1. 15.6.1. DDS-Based BIST Architecture
      2. 15.6.2. Frequency Response Test and Measurement
      3. 15.6.3. Linearity Test and Measurement
      4. 15.6.4. SNR and Noise Figure Measurement
    8. 15.7. Concluding Remarks
    9. 15.8. Exercises
    10. Acknowledgments
    11. References
      1. R15.0. Books
      2. R15.1. Introduction
      3. R15.2. Analog Functional Testing
      4. R15.3. Analog and Mixed-Signal Test Architectures
      5. R15.4. Defect-Oriented Mixed-Signal BIST Approaches
      6. R15.5. FFT-Based Mixed-Signal BIST
      7. R15.6. Direct Digital Synthesis BIST
  23. 16. RF Testing
    1. About This Chapter
    2. 16.1. Introduction
      1. 16.1.1. RF Basics
      2. 16.1.2. RF Applications
    3. 16.2. Key Specifications for RF Systems
      1. 16.2.1. Test Instrumentation
        1. 16.2.1.1. Spectrum Analyzer
        2. 16.2.1.2. Network Analyzer
        3. 16.2.1.3. Noise Figure Meter
        4. 16.2.1.4. Phase Meter
      2. 16.2.2. Test Flow in Industry
        1. 16.2.2.1. Design and Fabrication
        2. 16.2.2.2. Characterization Test
        3. 16.2.2.3. Production Test
      3. 16.2.3. Characterization Test and Production Test
        1. 16.2.3.1. Accuracy
        2. 16.2.3.2. Time Required for Testing
        3. 16.2.3.3. Cost of Testing
      4. 16.2.4. Circuit-Level Specifications
        1. 16.2.4.1. Gain
        2. 16.2.4.2. Harmonics and Third-Order Intercept Point (IP3)
        3. 16.2.4.3. 1-dB Compression Point (P–1dB)
        4. 16.2.4.4. Total Harmonic Distortion (THD)
        5. 16.2.4.5. Gain Flatness
        6. 16.2.4.6. Noise Figure
        7. 16.2.4.7. Sensitivity and Dynamic Range
        8. 16.2.4.8. Local Oscillator Leakage
        9. 16.2.4.9. Phase Noise
        10. 16.2.4.10. Adjacent Channel Power Ratio
      5. 16.2.5. System-Level Specifications
        1. 16.2.5.1. I-Q Mismatch
        2. 16.2.5.2. Error Vector Magnitude
        3. 16.2.5.3. Modulation Error Ratio
        4. 16.2.5.4. Bit Error Rate
      6. 16.2.6. Structure of RF Systems
    4. 16.3. Test Hardware: Tester and DIB/PIB
    5. 16.4. Repeatability and Accuracy
    6. 16.5. Industry Practices for High-Volume Manufacturing
      1. 16.5.1. Test Cost Analysis
      2. 16.5.2. Key Trends
    7. 16.6. Concluding Remarks
    8. 16.7. Exercises
    9. Acknowledgments
    10. References
      1. R16.0. Books
      2. R16.1. Introduction
      3. R16.2. Key Specifications for RF Systems
      4. R16.5. Industry Practices for High-Volume Manufacturing
  24. 17. Testing Aspects of Nanotechnology Trends
    1. About This Chapter
    2. 17.1. Introduction
    3. 17.2. Resonant Tunneling Diodes and Quantum-Dot Cellular Automata
      1. 17.2.1. Testing Threshold Networks with Application to RTDs
        1. Theorem 17.1
        2. Theorem 17.2
        3. Theorem 17.3
        4. Theorem 17.4
      2. 17.2.2. Testing Majority Networks with Application to QCA
    4. 17.3. Crossbar Array Architectures
      1. 17.3.1. Hybrid Nanoscale/CMOS Structures
        1. 17.3.1.1. The nanoPLA
        2. 17.3.1.2. Molecular CMOS (CMOL)
      2. 17.3.2. Built-In Self-Test
      3. 17.3.3. Simultaneous Configuration and Test
    5. 17.4. Carbon Nanotube (CNT) Field Effect Transistors
      1. 17.4.1. Imperfection-Immune Circuits for Misaligned CNTs
      2. 17.4.2. Robust Circuits for Metallic CNTs
    6. 17.5. Concluding Remarks
    7. Acknowledgments
    8. References
      1. R17.0. Books
      2. R17.1. Introduction
      3. R17.2. Resonant Tunneling Diodes and Quantum-Dot Cellular Automata
      4. R17.3. Crossbar Array Architectures
      5. R17.4. Carbon Nanotube (CNT) Field Effect Transistors