4.4 BIBLIOGRAPHY

[BRE1982] R. Brent and H. T. Kung, A regular layout for parallel adders. IEEE Trans. Comput., C-31(3): 260–264 (1982).

[HAN1987] T. Han and D. A. Carlson, Fast area-efficient VLSI adders. In: Proceedings of the 8th Symposium on Computer Arithmetic, 1987, pp. 49–56.

[KOG1973] P. M. Kogge and H. S. Stone, A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans. Comput., C-22(8): 786–793 (1973).

[LAD1980] R. E. Ladner and M. J. Fischer, Parallel prefix computation. J. ACM 27(10): 831–838 (1980).

[SUG1990] B. Sugla and D. Carlson, Extreme area-time tradeoffs in VLS. IEEE Trans. Comput. 39(2): 251–257 (1990).

Synthesis of Arithmetic Circuits: FPGA, ASIC, and Embedded Systems By Jean-Pierre Deschamps, Géry J. A. Bioul, and Gustavo D. SutterCopyright © 2006 John Wiley & Sons, Inc.

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