Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

16.9 COMMENTS

1. Unless the result r of an arithmetic operation is known to be included between either − x_max and − x_min, or x_min and x_max, an underflow (|r| < x_min) or overflow (|r| > x_max) could exist. The corresponding circuits should include additional components for detecting this type of situation. For example, the adder-subtractor of Figure 16.5 generates the signal zero_flag if the result is equal to 0.
2. A similar comment can be done if some special values (e.g., ∞, − ∞) must be represented.
3. The proposed circuits are straightforward implementations of the basic algorithms described in Section 16.2. A lot of improvements have been proposed in order to reduce the latency of the corresponding circuits. See, for example, [ERC2004] and [PAR2000].
4. The exponents e are integers included in some predefined interval e_min ≤ e ≤ e_max. Any type of representation can be used. For example (already mentioned in Chapter 3), in the ANSI/IEEE single-precision floating-point system the exponents are excess-127 integers.