12.3 BIBLIOGRAPHY
[BAU1973] C. R. Baugh and B. A. Wooley, A two's complement parallel array multiplication algorithm. IEEE Trans. Comput. C-22: 1045–1047 (1973).
[BIO2003] G. Bioul, J.-P. Deschamps, and G. Sutter. Spartan-II/Virtex Implementation of High Speed Adders. URJC Madrid, Technical Report, Feb. 2003.
[BOO1951] A. D. Booth, A signed binary multiplication technique. Q. J. Mech. Appl. Math. 4: 236–240 (1951).
[DAD1965] L. Dadda, Some schemes for parallel multipliers. Alta Frequenza 34: 349–356 (1965).
[DAV1977] M. Davio and G. Bioul, Fast parallel multiplication. Philips Res. Rpts. 32: 44–70 (1977).
[WAL1964] C. S. Wallace, A suggestion for fast multipliers. IEEE Trans. Electron. Comput. EC-13: 14–17 (1964).
Synthesis of Arithmetic Circuits: FPGA, ASIC, and Embedded SystemsBy Jean-Pierre Deschamps, Géry J. A. Bioul, and Gustavo D. SutterCopyright © 2006 John Wiley & Sons, Inc.
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