The SDH technique poses peculiar timing issues that deserve a closer look. Historically, the timing aspects of telecommunications networks have often been reduced to a set of pragmatic parameters and limits to verify, while their underlying rationale has not been normally considered part of the education of telecommunications engineers. The introduction of SDH has given a new perspective on timing and has yielded the need for a deeper insight, changing for example many of the original assumptions used in deriving such parameters and limits.
Moreover, new timing issues have been raised by SDH, which implies new phenomena generating jitter and wander, SDH further developed the concepts of asynchronous and synchronous digital transmission, as explained in the previous chapter. Hence the need for a closer look on the timing aspects of SDH.
This chapter deals with some of the key topics related to timing in SDH networks. First, the different causes of jitter and wander in an SDH transmission chain are reviewed. Then, the blocks where digital signals with asynchronous bit rates are arranged in SDH equipment are treated: the synchronizer, the desynchronizer and the pointer processor. Finally, the SDH equipment clock is described in terms of functional blocks.
In spite of the numerous advantages offered by SDH compared to PDH, SDH made the issue of controlling the jitter and wander of the transported ...