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Synchronization of Digital Telecommunications Networks

Book Description

Network synchronization deals with the distribution of time and frequency across a network of clocks often spread over a wide geographical area. The goal is to align (i.e. synchronize) the time and frequency scales of all clocks, by using the communication capacity of their interconnecting links.

Network synchronization plays a central role in digital telecommunications as it determines the quality of most services offered by the network operator. However, the importance of network synchronization is often underestimated and how to solve quality-of-service degradation caused by synchronization difficulties can become problematical to all but a synchronization engineer.

  • Systematically covers a wide spectrum of both theoretical and practical topics

  • Features a clear and profound description of synchronous and asynchronous digital multiplexing (PDH, SDH), jitter and timing aspects of SDH networks

  • Expounds synchronization network principles and implementation issues, clock modelling, time and frequency measurement

  • Presents recent advances in telecommunications clock characterization and measurement

If you are a system engineer, researcher, designer or postgraduate student searching for both the basics and an insight into more advanced areas currently under discussion then you will find Synchronization of Digital Telecommunications Networks an enlightening read. It will also prove to be a valuable sourcebook for senior undergraduates and technical personnel in telecommunications companies.

Table of Contents

  1. Coverpage
  2. Titlepage
  3. Copyright
  4. Contents
  5. Preface
  6. Acknowledgements
  7. Abbreviations
  8. Symbols
  9. 1 Introduction
    1. 1.1 Synchronization in Telecommunications
      1. 1.1.1 Carrier Synchronization
      2. 1.1.2 Symbol Synchronization
      3. 1.1.3 Frame Synchronization
      4. 1.1.4 Bit Synchronization
      5. 1.1.5 Packet Synchronization
      6. 1.1.6 Network Synchronization
      7. 1.1.7 Multimedia Synchronization
      8. 1.1.8 Synchronization of Real-Time Clocks
    2. 1.2 Outline of the Book
    3. 1.3 Summary
    4. 1.4 References
  10. 2 Asynchronous and Synchronous Digital Multiplexing
    1. 2.1 Basic Concepts
      1. 2.1.1 Timing Signals and Digital Signals
      2. 2.1.2 Timing Relationships between Digital Signals
      3. 2.1.3 Jitter and Wander
      4. 2.1.4 Asynchronous vs Synchronous Transfer Modes
      5. 2.1.5 Taxonomy of Multiplexing Techniques
      6. 2.1.6 Time Division Multiplexing (TDM)
    2. 2.2 The PCM Primary Multiplex
    3. 2.3 Digital Multiplexing
      1. 2.3.1 Synchronous Digital Multiplexing
      2. 2.3.2 Slips
      3. 2.3.3 Synchronous Digital Multiplexer and Demultiplexer
      4. 2.3.4 Asynchronous Digital Multiplexing: Bit Justification
      5. 2.3.5 Asynchronous Digital Multiplexer and Demultiplexer
    4. 2.4 The Plesiochronous Digital Hierarchies (PDH)
      1. 2.4.1 The European Plesiochronous Digital Hierarchy (Ei)
      2. 2.4.2 The North American and Japanese Plesiochronous Digital Hierarchies (DSi/Ti)
    5. 2.5 The Synchronous Digital Hierarchy (SDH) and SONET
      1. 2.5.1 A Bit of History
      2. 2.5.2 Hierarchical Levels of SDH and SONET
      3. 2.5.3 SDH Frame Structure
      4. 2.5.4 Synchronous Multiplexing in SDH
      5. 2.5.5 Synchronous Multiplexing Elements
      6. 2.5.6 Example of PDH Signal Transport on SDH: Asynchronous Mapping of the 139.264 Mbit/s
      7. 2.5.7 Example of PDH Signal Transport on SDH: Asynchronous Mapping of the 2.048 Mbit/s
      8. 2.5.8 The Pointer Justification Mechanism: Synchronous Multiplexing in Asynchronous Networks
      9. 2.5.9 SDH Equipment
      10. 2.5.10 ITU-T Standards on SDH
      11. 2.5.11 Summary of Characteristics of the SDH Signals
    6. 2.6 Asynchronous vs Synchronous Multiplex Frame Structures
    7. 2.7 Summary
    8. 2.8 References
  11. 3 Timing Aspects in SDH Networks
    1. 3.1 Causes of Jitter and Wander in an SDH Transmission Chain
      1. 3.1.1 Environmental Conditions (Temperature)
      2. 3.1.2 Overhead and Fixed Stuffing in the Mapping Structure
      3. 3.1.3 Bit Justification
      4. 3.1.4 Pointer Justification
    2. 3.2 Synchronization Processes Along an SDH Transmission Chain
      1. 3.2.1 Mapping of the PDH Tributary into SDH Frames
      2. 3.2.2 Re-Synchronization of the VCs in SDH Intermediate Nodes
      3. 3.2.3 Demapping of the PDH Tributary from SDH Frames
      4. 3.2.4 The Average Frequency of Tributary Signals Is Transferred along the Chain
    3. 3.3 SDH Synchronizer and Desynchronizer
      1. 3.3.1 Principle of Operation of an SDH Synchronizer
      2. 3.3.2 Principle of Operation of an SDH Desynchronizer
      3. 3.3.3 Phase-Locked Loops Used in Desynchronizers for Jitter Reduction
      4. 3.3.4 Enhanced Design of Synchronizers: Stuff Threshold Modulation
      5. 3.3.5 Enhanced Design of Desynchronizers: Reducing Pointer Adjustment Jitter by Bit Leaking
    4. 3.4 SDH Pointer Processor
      1. 3.4.1 Basic Pointer Processor
      2. 3.4.2 Advanced Pointer Processors
    5. 3.5 The SDH Equipment Clock
      1. 3.5.1 ITU-T Functional Description
      2. 3.5.2 Timing Modes
      3. 3.5.3 External Synchronization Physical Interface
    6. 3.6 Summary
    7. 3.7 References
  12. 4 Network Synchronization Architectures
    1. 4.1 An Historical Perspective on Network Synchronization
      1. 4.1.1 Synchronization in Analogue FDM Networks
      2. 4.1.2 Synchronization and PDH Digital Transmission
      3. 4.1.3 Synchronization and Digital Switching
      4. 4.1.4 Impact of Slips on Digital Services
      5. 4.1.5 Synchronization of Digital-Switching Equipment across PDH Links
      6. 4.1.6 Synchronization and SDH/SONET Digital Transmission
      7. 4.1.7 Synchronization in ATM Transport Networks
      8. 4.1.8 Synchronization of Cellular Mobile Wireless Telephone Networks
      9. 4.1.9 Synchronization Today and Beyond
    2. 4.2 Network Synchronization Strategies
      1. 4.2.1 Full Plesiochrony (Anarchy)
      2. 4.2.2 Master–Slave Synchronization (Despotism)
      3. 4.2.3 Mutual Synchronization (Democracy)
      4. 4.2.4 Mixed Mutual/Master–Slave Synchronization (Oligarchy)
      5. 4.2.5 Hierarchical Mutual Synchronization (Hierarchical Democracy)
      6. 4.2.6 Hierarchical Master–Slave Synchronization (Hierarchical Despotism)
      7. 4.2.7 Mixed Plesiochronous/Synchronous Networks (Independent Despotic States)
    3. 4.3 Standard Architectures of Synchronization Network
      1. 4.3.1 The ETSI and ITU-T Synchronization Network Architecture
      2. 4.3.2 The ANSI Synchronization Network Architecture
    4. 4.4 Synchronization Network Planning
      1. 4.4.1 General Guidelines
      2. 4.4.2 Intra-Node Timing Distribution: the BITS/SASE concept
      3. 4.4.3 Guidelines for Inter-Node Timing Distribution
      4. 4.4.4 Synchronization Network Planning in SDH and SONET Networks
    5. 4.5 Synchronization Network Management
      1. 4.5.1 Functional Areas and Abstraction Levels of Network Management
      2. 4.5.2 TMN Management
      3. 4.5.3 TMN Functional Architecture, Reference Points and Interfaces
      4. 4.5.4 Management Systems for Synchronization Networks
    6. 4.6 Synchronization Network Performance Monitoring
      1. 4.6.1 Synchronization Failures and Impairments
      2. 4.6.2 Strategies for Synchronization Network Performance Monitoring
      3. 4.6.3 Methods for Synchronization Network Performance Monitoring
    7. 4.7 Synchronization Network Protection: Synchronization Status Messaging
      1. 4.7.1 Criteria for Designing a Synchronization Protection Algorithm
      2. 4.7.2 Synchronization Status Messages
      3. 4.7.3 Synchronization Status Messages in SDH Networks
      4. 4.7.4 Synchronization Status Messages in SONET Networks
      5. 4.7.5 Synchronization Status Messages in PDH Networks
      6. 4.7.6 Rules for Selecting the Active Reference after Failure
      7. 4.7.7 Basic Rules for SSM Generation
      8. 4.7.8 Example of Automatic Synchronization Protection in an SDH Ring by Use of Synchronization Status Messages
    8. 4.8 Examples of Synchronization Networks
      1. 4.8.1 The Synchronization Network of AT&T (USA)
      2. 4.8.2 The Synchronization Network of Swiss PTT
      3. 4.8.3 The Synchronization Network of NTT (Japan)
      4. 4.8.4 The Synchronization Network of France Telecom
      5. 4.8.5 The Synchronization Network of Telecom Argentina
      6. 4.8.6 Synchronization of the Telephone Digital Switching Network of Telecom Italia
      7. 4.8.7 The New Synchronization Network of Telecom Italia
    9. 4.9 Summary
    10. 4.10 References
  13. 5 Characterization and Modelling of Clocks
    1. 5.1 Clocks and Timing Signals
    2. 5.2 Timing Signal Model and Basic Quantities
    3. 5.3 Basic Concepts of Quality of Clocks: Stability and Accuracy
      1. 5.3.1 Stability
      2. 5.3.2 Accuracy
    4. 5.4 Autonomous Clocks
    5. 5.5 Slave Clocks
      1. 5.5.1 Phase-Locked Loop Fundamentals
      2. 5.5.2 Second-Order Phase-Locked Loop
      3. 5.5.3 Third-Order, Type-3 Phase-Locked Loop
      4. 5.5.4 PLL Performance with Input Additive Noise
      5. 5.5.5 PLL Performance with Internal Noise Sources
      6. 5.5.6 Operational Ranges of Slave Clocks
      7. 5.5.7 Operation Modes of Slave Clocks in a Synchronization Network
    6. 5.6 Frequency-Domain and Time-Domain Stability Characterization
    7. 5.7 Clock Stability Characterization in the Frequency Domain
      1. 5.7.1 Power Spectral Density of the Timing Signal
      2. 5.7.2 Power Spectral Densities of Phase and Frequency Fluctuations
      3. 5.7.3 Other Spectral Measures
    8. 5.8 Clock Stability Characterization in the Time Domain
      1. 5.8.1 Basic Measurement of y (t) in the Time Domain
      2. 5.8.2 Classical Variance of y(t) (True Variance)
      3. 5.8.3 M -Sample Variance of y (t)
      4. 5.8.4 Allan Variance
      5. 5.8.5 Modified Allan Variance
      6. 5.8.6 Time Variance (TVAR)
      7. 5.8.7 Root Mean Square of the Time Interval Error (TlErms)
      8. 5.8.8 Maximum Time Interval Error
      9. 5.8.9 Standard Estimators of Stability Quantities Defined in ITU-T Recommendations and ETSI Standards
      10. 5.8.10 Translation from Frequency-Domain to Time-Domain Measures
      11. 5.8.11 Hadmard variance
    9. 5.9 Common Types of Clock Noise
      1. 5.9.1 Power-Law Noise
      2. 5.9.2 Periodic Noise
      3. 5.9.3 Background White Phase Noise Due to ΊΊrigger and Quantization Errors
    10. 5.10 Behaviour of the Time-Domain Stability Quantities: Autonomous Clocks
      1. 5.10.1 Power-Law Noise
      2. 5.10.2 Frequency Offset and Drift
      3. 5.10.3 Periodic Noise
    11. 5.11 Behaviour of the Time-Domain Stability Quantities: Slave Clocks
    12. 5.12 Chains of Slave Clocks
    13. 5.13 Summary
    14. 5.14 References
    15. Appendix 5A Fast Computation of TVAR Estimator by Recursion Algorithm
    16. Appendix 5B Fast Computation of MTIE Estimator by Binary Decomposition
      1. 5B.1 Plain Computation of MTIE Estimator
      2. 5B.2 MTIE Computation by Binary Decomposition
      3. 5B.3 Computational Saving
  14. 6 Physical Principles and Technology of Clocks
    1. 6.1 Clocks
    2. 6.2 Quartz-Crystal Oscillators
      1. 6.2.1 Plain Crystal Oscillators
      2. 6.2.2 Voltage-Controlled Crystal Oscillators
      3. 6.2.3 Temperature-Compensated Crystal Oscillators
      4. 6.2.4 Oven-Controlled Crystal Oscillators
      5. 6.2.5 Performance and Characteristics of Crystal Oscillators
    3. 6.3 Atomic Frequency Standards
      1. 6.3.1 Physical Principle of Operation
      2. 6.3.2 Caesium-Beam Frequency Standard
      3. 6.3.3 Hydrogen-MASER Frequency Standard
      4. 6.3.4 Rubidium-Gas-Cell Frequency Standard
      5. 6.3.5 Performance and Characteristics of Atomic Frequency Standards
    4. 6.4 The Global Positioning System
      1. 6.4.1 How Does GPS Work
      2. 6.4.2 Space Segment
      3. 6.4.3 NAVSTAR Control Segment
      4. 6.4.4 User Segment
      5. 6.4.5 NAVSTAR GPS Signals
      6. 6.4.6 NAVSTAR Standard and Precise Positioning Services
      7. 6.4.7 Differential GPS
      8. 6.4.8 Use of GPS for Time and Frequency Dissemination
    5. 6.5 Summary
    6. 6.6 References
  15. 7 Time and Frequency Measurement Techniques in Telecommunications
    1. 7.1 Basic Concepts
      1. 7.1.1 Measuring the Power Spectral Density of the Timing Signal (RF Power Spectrum)
      2. 7.1.2 Quantities Recommended by IEEE for Frequency Stability Measurement
      3. 7.1.3 Quantities Defined in International Standards and Their Estimators
      4. 7.1.4 Hierarchy of Time and Frequency Measurement Techniques
      5. 7.1.5 Estimating of the Frequency Offset and Linear Drift
      6. 7.1.6 Confidence of the Allan Variance Estimate
      7. 7.1.7 Separating the Variances of the Clock under Test and of the Reference Clock
      8. 7.1.8 Measuring Frequency Stability in the Independent and in the Synchronized Clock Configuration
      9. 7.1.9 Impact of the TE Sampling Period on the Behaviour of the Stability Quantities
    2. 7.2 Instrumentation for Time and Frequency Measurement in Telecommunications
      1. 7.2.1 Low-Noise Mixer
      2. 7.2.2 Frequency Synthesizer
      3. 7.2.3 Analogue and Digital Spectrum Analysers
      4. 7.2.4 Digital Time Counter
    3. 7.3 Direct Digital Measurement
      1. 7.3.1 Measurement of Time Intervals (Direct Digital Measurement of Time Error)
      2. 7.3.2 Measurement of the Frequency
      3. 7.3.3 Measurement of the Period
      4. 7.3.4 Techniques for Enhancing the Measurement Sensitivity
    4. 7.4 Heterodyne Techniques: The Beat-Frequency Method
    5. 7.5 Homodyne Techniques
      1. 7.5.1 Delay-Line Methods
      2. 7.5.2 Phase-Locked Loop Methods
    6. 7.6 Multiple Conversion Techniques
      1. 7.6.1 Frequency Synthesis
      2. 7.6.2 The Dual-Mixer Time-Difference Technique
    7. 7.7 Clock Stability Measurement in Telecommunications
      1. 7.7.1 Distinctive Features
      2. 7.7.2 Practical Measurement Procedure by Acquisition of Sequences of Time Error Samples
      3. 7.7.3 Measurement of Maximum Time Interval Error
    8. 7.8 Other Measurements on Equipment Clocks
      1. 7.8.1 Output Jitter
      2. 7.8.2 Jitter Tolerance
      3. 7.8.3 Jitter Transfer Function
      4. 7.8.4 Hold-in, Pull-out, Lock-in and Pull-in Ranges
      5. 7.8.5 Output Phase Transients
    9. 7.9 Network Measurements
    10. 7.10 Summary
    11. 7.11 References
    12. Appendix 7A: Experimental Set-Up and Procedure Followed for Measurement Results Shown in Chapters 5 and 7
  16. Glossary of Terms
  17. Index