Synchronization and Arbitration in Digital Systems

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Conclusions Part II

Systems on silicon are increasingly made of a number of independently timed core processors connected together by a communications network. Data passing between two of these processors needs to be retimed to allow it to pass between them safely, but the synchronization techniques that can be used depend on the timing relationship between the sender and the receiver.

In a synchronous system the timing of each process is usually driven by a single common clock. In a mesochronous system the clocks are more loosely linked by being phase locked to a common source so that phase can drift more widely, but within some bound. If the two clocks are effectively locked together in this way, the methods described in Section 7.3 avoid the need for conventional synchronization, and the latency of the interface can be small. In a plesiochronous system each processor may have its own autonomous clock, and Section 7.4 shows how data can be synchronized again, with relatively low latency if the clocks are similar in frequency, but the phase relationship is unbounded.

Latency and throughput are issues with more conventional synchronizers when the clock relationship between the two sides of an interface are unknown. In Section 7.1 a simple synchronizing interface is shown to have a relatively slow throughput, but throughput can be improved, usually at the expense of latency by adding a FIFO as in Section 7.2.

Relatively low-performance systems may not need a full clock cycle ...