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Silicon-On-Insulator (SOI) Technology

Book Description

Silicon-On-Insulator (SOI) Technology: Manufacture and Applications covers SOI transistors and circuits, manufacture, and reliability. The book also looks at applications such as memory, power devices, and photonics.

Table of Contents

  1. Cover image
  2. Title page
  3. Copyright
  4. Contributor contact details
  5. Woodhead Publishing Series in Electronic and Optical Materials
  6. Introduction
  7. Part I: Silicon-on-insulator (SOI) materials and manufacture
    1. 1. Materials and manufacturing techniques for silicon-on-insulator (SOI) wafer technology
      1. Abstract:
      2. 1.1 Introduction
      3. 1.2 SOI wafer fabrication technologies: an overview
      4. 1.3 SOI volume-fabrication process
      5. 1.4 SOI wafer structures and characterization
      6. 1.5 Direct wafer bonding: wet surface cleaning techniques
      7. 1.6 Characterization of direct bonding mechanisms
      8. 1.7 Alternative surface preparation processes for Si and SiO<sub xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">2</sub> direct bonding direct bonding
      9. 1.8 Mass production of SOI substrates by ion implantation, bonding and splitting: Smart Cut™ technology
      10. 1.9 Fabrication of more complex SOI structures
      11. 1.10 Fabrication of heterogeneous structures
      12. 1.11 Conclusion
      13. 1.12 Acknowledgments
      14. 1.13 References
    2. 2. Characterization of the electrical properties of advanced silicon-on-insulator (SOI) materials and transistors
      1. Abstract:
      2. 2.1 Introduction
      3. 2.2 Conventional characterization techniques
      4. 2.3 Characterization of SOI wafers using the pseudo-metal oxide semiconductor field effect transister (MOSFET) technique
      5. 2.4 Developments in the pseudo-MOSFET technique
      6. 2.5 Conventional methods for the characterization of FD MOSFETs
      7. 2.6 Advanced methods for the characterization of FD MOSFETs
      8. 2.7 Characterization of ultrathin SOI MOSFETs
      9. 2.8 Characterization of multiple-gate MOSFETs
      10. 2.9 Characterization of nanowire FETs
      11. 2.10 Conclusions
      12. 2.11 Acknowledgments
      13. 2.12 References
    3. 3. Modeling the performance of short-channel fully depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs)
      1. Abstract:
      2. 3.1 Introduction
      3. 3.2 The development of SOI MOSFET modeling
      4. 3.3 A 1-D compact capacitive model for a SOI MOSFET
      5. 3.4 A 2-D analytical model for a SOI MOSFET
      6. 3.5 Modeling of dual gate and other types of SOI MOSFET architecture
      7. 3.6 References
    4. 4. Partially depleted (PD) silicon-on-insulator (SOI) technology: circuit solutions
      1. Abstract:
      2. 4.1 Introduction
      3. 4.2 PDSOI technology and devices
      4. 4.3 Circuit solutions: digital circuits
      5. 4.4 Circuit solutions: static random access memory (SRAM) circuits
      6. 4.5 SRAM margining: PDSOI example
      7. 4.6 Future trends
      8. 4.7 References
    5. 5. Planar fully depleted (FD) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology
      1. Abstract:
      2. 5.1 Introduction
      3. 5.2 Planar FDSOI technology
      4. 5.3 <em xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">V</em><sub xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops"><em>T</em></sub> adjustment on FDSOI: channel doping, gate stack engineering and ground planes adjustment on FDSOI: channel doping, gate stack engineering and ground planes
      5. 5.4 Substrate requirements for FDSOI CMOS devices: BOX and channel thicknesses
      6. 5.5 Strain options on FDSOI
      7. 5.6 Performance without and with back bias
      8. 5.7 Conclusion
      9. 5.8 Acknowledgements
      10. 5.9 References
    6. 6. Silicon-on-insulator (SOI) junctionless transistors
      1. Abstract:
      2. 6.1 Introduction
      3. 6.2 Device physics
      4. 6.3 Models for the junctionless transistor
      5. 6.4 Performance comparison with trigate field effect transistors (FETs)
      6. 6.5 Beyond the classical SOI nanowire architecture
      7. 6.6 Conclusion
      8. 6.7 Acknowledgments
      9. 6.8 References
    7. 7. Silicon-on-insulator (SOI) fin-on-oxide field effect transistors (FinFETs)
      1. Abstract:
      2. 7.1 Introduction
      3. 7.2 SOI FinFET device performance
      4. 7.3 SOI FinFET substrate optimization
      5. 7.4 Process and statistical variability of FinFETs
      6. 7.5 Summary
      7. 7.6 References
    8. 8. Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology
      1. Abstract:
      2. 8.1 Introduction
      3. 8.2 Statistical variability in planar fully depleted SOI devices
      4. 8.3 Statistical aspects of reliability
      5. 8.4 Fin-on-oxide field effect transistors (FinFETs) on SOI
      6. 8.5 Summary and future trends
      7. 8.6 References
    9. 9. Protecting against electrostatic discharge (ESD) in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) manufactured using silicon-on-insulator (SOI) technology
      1. Abstract:
      2. 9.1 Introduction
      3. 9.2 ESD characterization in SOI devices: SOI transistors
      4. 9.3 ESD characterization in SOI devices: SOI diodes
      5. 9.4 ESD characterization in SOI devices: fin-on-oxide field effect transistors (FinFETs) and FinDiodes
      6. 9.5 ESD characterization in SOI devices: fully depleted SOI (FDSOI) devices
      7. 9.6 ESD network optimization in SOI devices
      8. 9.7 Conclusion
      9. 9.8 References
  8. Part II: Silicon-on-insulator (SOI) devices and applications
    1. 10. Silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) for radio frequency (RF) and analogue applications
      1. Abstract:
      2. 10.1 Introduction
      3. 10.2 Current performance of RF devices
      4. 10.3 Limiting factors in MOSFET performance
      5. 10.4 Schottky barrier (SB) MOSFETs
      6. 10.5 Ultra-thin body ultra-thin BOX (UTBB) MOSFETs
      7. 10.6 RF performance of a multi-gate MOSFET: fin-on-oxide field effect transistor (FinFET)
      8. 10.7 High-resistivity silicon (HR-Si) substrate for SOI technology
      9. 10.8 Conclusions
      10. 10.9 Acknowledgements
      11. 10.10 References
    2. 11. Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits for ultralow power (ULP) applications
      1. Abstract:
      2. 11.1 Introduction: the importance of ultralow power devices
      3. 11.2 Minimizing power consumption of CMOS circuits
      4. 11.3 Issues on <em xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">V</em><sub xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops">dd</sub> scaling to improve the energy efficiency of CMOS circuits scaling to improve the energy efficiency of CMOS circuits
      5. 11.4 Developing SOI devices with small variability and adaptive bias control
      6. 11.5 Modelling variability
      7. 11.6 Device design for ultralow-voltage operation
      8. 11.7 Assessing variability in fully depleted silicon-on-insulator (FDSOI) devices
      9. 11.8 Assessing the reliability of FDSOI devices
      10. 11.9 Circuit design of FDSOI devices
      11. 11.10 Future trends
      12. 11.11 Acknowledgment
      13. 11.12 References
    3. 12. 3D integration of silicon-on-insulator (SOI) integrated circuits (ICs) for improved performance
      1. Abstract:
      2. 12.1 Introduction
      3. 12.2 3D integration using Cu–Cu bonding: generic flow techniques
      4. 12.3 3D integration using Cu–Cu bonding: face-to face silicon layer stacking
      5. 12.4 3D integration using Cu–Cu bonding: back-to-face silicon layer stacking
      6. 12.5 3D integration using oxide bonding: the MIT Lincoln Laboratory’s ‘face down’ stacking technique
      7. 12.6 3D integration using oxide bonding: IBM’s ‘face up’ stacking technique
      8. 12.7 3D integration using oxide bonding: the sequential 3D process
      9. 12.8 Advanced bonding technology: Cu–Cu bonding
      10. 12.9 Advanced bonding technology: dielectric bonding
      11. 12.10 Summary
      12. 12.11 Acknowledgements
      13. 12.12 References
    4. 13. Silicon-on-insulator (SOI) technology for photonic integrated circuits (PICs)
      1. Abstract:
      2. 13.1 Introduction
      3. 13.2 Silicon (on insulator) photonics
      4. 13.3 Photonic building blocks in SOI
      5. 13.4 Device tolerances and compensation techniques
      6. 13.5 Advanced stacks for silicon photonics
      7. 13.6 Applications of silicon photonics
      8. 13.7 Conclusion
      9. 13.8 References
    5. 14. Silicon-on-insulator (SOI) technology for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) sensors
      1. Abstract:
      2. 14.1 Introduction
      3. 14.2 SOI MEMS/NEMS device structures and principles of operation
      4. 14.3 SOI MEMS/NEMS design
      5. 14.4 SOI MEMS/NEMS processing technologies
      6. 14.5 SOI MEMS/NEMS fabrication
      7. 14.6 Conclusion
      8. 14.7 References
  9. Index