See MIPS Run, 2nd Edition

See MIPS Run, 2nd Edition

by Dominic Sweetman
Released July 2010
Publisher(s): Morgan Kaufmann
ISBN: 9780080525235

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Book description

See MIPS Run, Second Edition, is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux.

Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.

  • Completely new material offers the best explanation available on how Linux runs on real hardware
  • Provides a complete, updated and easy-to-use guide to the MIPS instruction set using the MIPS32 standard as the baseline architecture with the MIPS64 as the main option
  • Retains the same engaging writing style that made the first edition so readable, reflecting the authors 20+ years experience in designing systems based on the MIPS architecture

Table of contents

  1. Cover
  2. Title Page
  3. Copyright
  4. Foreword
  5. Preface
    1. Style and Limits
    2. Conventions
    3. Acknowledgments
  6. Table of Contents
  7. Chapter 1: RISCs and MIPS Architectures
    1. 1.1 Pipelines
    2. 1.2 The MIPS Five-Stage Pipeline
    3. 1.3 RISC and CISC
    4. 1.4 Great MIPS Chips of the Past and Present
    5. 1.5 MIPS Compared with CISC Architectures
  8. Chapter 2: MIPS Architecture
    1. 2.1 A Flavor of MIPS Assembly Language
    2. 2.2 Registers
    3. 2.3 Integer Multiply Unit and Registers
    4. 2.4 Loading and Storing: Addressing Modes
    5. 2.5 Data Types in Memory and Registers
    6. 2.6 Synthesized Instructions in Assembly Language
    7. 2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions
    8. 2.8 Basic Address Space
    9. 2.9 Pipeline Visibility
  9. Chapter 3: Coprocessor 0: MIPS Processor Control
    1. 3.1 CPU Control Instructions
    2. 3.2 Which Registers Are Relevant When?
    3. 3.3 CPU Control Registers and Their Encoding
    4. 3.4 CP0 Hazards—A Trap for the Unwary
  10. Chapter 4: How Caches Work on MIPS Processors
    1. 4.1 Caches and Cache Management
    2. 4.2 How Caches Work
    3. 4.3 Write-Through Caches in Early MIPS CPUs
    4. 4.4 Write-Back Caches in MIPS CPUs
    5. 4.5 Other Choices in Cache Design
    6. 4.6 Managing Caches
    7. 4.7 L2 and L3 Caches
    8. 4.8 Cache Configurations for MIPS CPUs
    9. 4.9 Programming MIPS32/64 Caches
    10. 4.10 Cache Efficiency
    11. 4.11 Reorganizing Software to Influence Cache Efficiency
    12. 4.12 Cache Aliases
  11. Chapter 5: Exceptions, Interrupts, and Initialization
    1. 5.1 Precise Exceptions
    2. 5.2 When Exceptions Happen
    3. 5.3 Exception Vectors: Where Exception Handling Starts
    4. 5.4 Exception Handling: Basics
    5. 5.5 Returning from an Exception
    6. 5.6 Nesting Exceptions
    7. 5.7 An Exception Routine
    8. 5.8 Interrupts
    9. 5.9 Starting Up
    10. 5.10 Emulating Instructions
  12. Chapter 6: Low-level Memory Management and the TLB
    1. 6.1 The TLB/MMU Hardware and What It Does
    2. 6.2 TLB/MMU Registers Described
    3. 6.3 TLB/MMU Control Instructions
    4. 6.4 Programming the TLB
    5. 6.5 Hardware-Friendly Page Tables and Refill Mechanism
    6. 6.6 Everyday Use of the MIPS TLB
    7. 6.7 Memory Management in a Simpler OS
  13. Chapter 7: Floating-Point Support
    1. 7.1 A Basic Description of Floating Point
    2. 7.2 The IEEE 754 Standard and Its Background
    3. 7.3 How IEEE Floating-Point Numbers Are Stored
    4. 7.4 MIPS Implementation of IEEE 754
    5. 7.5 Floating-Point Registers
    6. 7.6 Floating-Point Exceptions/Interrupts
    7. 7.7 Floating-Point Control: The Control/Status Register
    8. 7.8 Floating-Point Implementation Register
    9. 7.9 Guide to FP Instructions
    10. 7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE
    11. 7.11 Instruction Timing Requirements
    12. 7.12 Instruction Timing for Speed
    13. 7.13 Initialization and Enabling on Demand
    14. 7.14 Floating-Point Emulation
  14. Chapter 8: Complete Guide to the MIPS Instruction Set
    1. 8.1 A Simple Example
    2. 8.2 Assembly Instructions and What They Mean
    3. 8.3 Floating-Point Instructions
    4. 8.4 Differences in MIPS32/64 Release 1
    5. 8.5 Peculiar Instructions and Their Purposes
    6. 8.6 Instruction Encodings
    7. 8.7 Instructions by Functional Group
  15. Chapter 9: Reading MIPS Assembly Language
    1. 9.1 A Simple Example
    2. 9.2 Syntax Overview
    3. 9.3 General Rules for Instructions
    4. 9.4 Addressing Modes
    5. 9.5 Object File and Memory Layout
  16. Chapter 10: Porting Software to the MIPS Architecture
    1. 10.1 Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems
    2. 10.2 Endianness: Words, Bytes, and Bit Order
    3. 10.3 Trouble with Visible Caches
    4. 10.4 Memory Access Ordering and Reordering
    5. 10.5 Writing it in C
  17. Chapter 11: MIPS Software Standards (ABIs)
    1. 11.1 Data Representations and Alignment
    2. 11.2 Argument Passing and Stack Conventions for MIPS ABIs
  18. Chapter 12: Debugging MIPS Designs—Debug and Profiling Features
    1. 12.1 The “EJTAG” On-chip Debug Unit
    2. 12.2 Pre-EJTAG Debug Support—Break Instruction and CPO Watchpoints
    3. 12.3 PDtrace
    4. 12.4 Performance Counters
  19. Chapter 13: GNU/Linux from Eight Miles High
    1. 13.1 Components
    2. 13.2 Layering in the Kernel
  20. Chapter 14: How Hardware and Software Work Together
    1. 14.1 The Life and Times of an Interrupt
    2. 14.2 Threads, Critical Regions, and Atomicity
    3. 14.3 What Happens on a System Call
    4. 14.4 How Addresses Get Translated in Linux/MIPS Systems
  21. Chapter 15: MIPS Specific Issues in the Linux Kernel
    1. 15.1 Explicit Cache Management
    2. 15.2 CP0 Pipeline Hazards
    3. 15.3 Multiprocessor Systems and Coherent Caches
    4. 15.4 Demon Tweaks for a Critical Routine
  22. Chapter 16: Linux Application Code, PIC, and Libraries
    1. 16.1 How Link Units Get into a Program
    2. 16.2 Global Offset Table (GOT) Organization
  23. Appendix A: MIPS Multithreading
    1. A.1 What Is Multithreading?
    2. A.2 Why Is MT Useful?
    3. A.3 How to Do Multithreading for MIPS
    4. A.4 MT in Action
  24. Appendix B: Other Optional Extensions to the MIPS Instruction Set
    1. B.1 MIPS16 and MIPS16e ASEs
    2. B.2 The MIPS DSP ASE
    3. B.3 The MDMX ASE
  25. MIPS Glossary
  26. References
    1. Books and Articles
    2. Online Resources
  27. Index

Product information

  • Title: See MIPS Run, 2nd Edition
  • Author(s): Dominic Sweetman
  • Release date: July 2010
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080525235