There is one situation that we didn't see how to solve, though. When our processor receives a conditional jump instruction, depending on the current state of the processor flags, the next instruction to execute will be one or another. This means that we cannot anticipate some instructions and load them into the pipeline. Or can we?
There are multiple ways of somehow predicting what code will be run next without doing the computation of the last instructions. The simplest way, and one used in old processors, was to statically decide which branches will load the next instructions and which will load instructions at the jump address.
Some processors would do that by deciding that some type of instructions were more likely to ...
