# 2.4 Sampling Jitter

In a modern transceiver, the DAC and ADC delimit the boundary between the digital and analog parts of the signal processing. The clocks used to sample the signal are not ideal and introduce error on the sampling time which manifests itself as noise and can limit the system performance. This timing error is known as jitter, and is expressed in seconds.

## 2.4.1 Jitter Definitions

A real oscillator will always suffer from phase noise (in the frequency domain), which can equivalently be described as jitter in the time domain reflecting random fluctuations in period (Drakhlis, 2001; Mansuri and Yang, 2002). If we define *T*_{0} as the mean period of the oscillator (generally approximated as the ideal one) and its *n*th period as *T*_{n}, the period error Δ*T*_{n} = (*T*_{n} − *T*_{0}) is called *period jitter* or *cycle jitter* (Silicon Laboratories, 2006) and is generally defined with its STD value:

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Cycle jitter compares the oscillating period with the mean period, while *cycle-to-cycle jitter* compares each period with the preceding period. Cycle-to-cycle jitter describes the short-term dynamics of the period; its STD is given by

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Another definition which is very important in communication systems is the *cumulative jitter* (Awad, 1995) because it is function of time as opposed to period and ...