Reliability of emerging nanodevices
N. Raghavan; K.L. Pey Singapore University of Technology and Design (SUTD), Singapore
Abstract
This chapter describes the various failure mechanisms that degrade the reliability of nanoelectronic logic and memory devices and systems. The first part deals with the evolution in semiconductor technology over the past decade in terms of new material and device architectures that are being explored. Following this, the key failure mechanisms at the front end, back end, and package level for logic technology and their driving forces are discussed in-depth along with a brief overview of degradation metrics in nonvolatile memory devices as well. Finally, the challenges that we face in establishing a robust reliability ...
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