Reconfigurable Computing

Chapter 18. Retiming, Repipelining, and C-slow Retiming

Nicholas WeaverInternational Computer Science Institute

Although pipelining is a huge benefit in field-programmable gate array (FPGA) designs, and may be required on some FPGA fabrics [5, 10, 12], it is often difficult for a designer to manage and balance pipeline stages and to insert the necessary delays to meet design requirements.

Leiserson et al. [4] were the first to propose retiming, an automatic process to relocate pipeline stages to balance a design. Their algorithm, in O(n²lg(n)) time, can rebalance a design so that the critical path is optimally pipelined. In addition, two modifications, repipelining and C-slow retiming, can add additional pipeline stages to a design to further improve ...