O'Reilly logo

Real-Time Digital Signal Processing by Nasser Kehtarnavaz

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

CHAPTER 5

Interrupt Data Processing

On a DSP processor, the processing of samples can be done within an ISR (interrupt service routine). Let us first discuss interrupts. As the name implies, an interrupt causes the processor to halt whatever it is processing in order to execute an ISR. An interrupt can be issued externally or internally. Twelve CPU interrupts are available on the C6x processor. The priorities of these interrupts are shown in Table 5-1. RESET is the highest priority interrupt. It halts the CPU and initializes all the registers to their default values. Non-maskable interrupt (NMI) is used for non-maskable or uninterruptible processing provided that the NMIE bit of the control register CSR (control status register) is set to ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required