RapidIO: The Next Generation Communication Fabric For Embedded Application

2.11. THE SERIAL PHYSICAL LAYER

Since the Serial RapidIO specification is defined only in the physical layer (the RapidIO technology defines the physical layer as the electrical interface and the device to device link protocol), most of the RapidIO controller logic remains the same. As a result, much of the design knowledge and verification infrastructure are preserved. This also eases system level switching between parallel and serial links.

During the initial development stages of the Serial RapidIO specifications the committee decided to try and preserve as many of the concepts found in the RapidIO parallel specifica-tion as possible. The parallel specification includes the concept of packets and in-band control symbols. These were delineated and differentiated by both a separate frame signal and an S bit in the header. In the serial link specification this delineation is accomplished using spare characters (K codes) found in the 8B/10B encoding. In this way, the sending device indicates to the receiving link partner the start of a packet, end of packet or start of control symbol using these codes as delimiting markers. More details on this are provided in Chapter 7.

2.11.1. PCS and PMA Layers

The Serial RapidIO specification uses a physical coding sublayer (PCS) and physical media attachment (PMA) sublayer to organize packets into a serial bit stream at the sending side and to extract the bit stream at the receiving side (this terminology is adopted from IEEE 802.3 Ethernet ...