RapidIO: The Next Generation Communication Fabric For Embedded Application

9.4. RAPIDIO TO PCI TRANSACTION MAPPING

The RapidIO Logical Input/Output and Globally Shared Memory specifications include the necessary transactions types to map all PCI transactions. Table 9.1 lists the mapping of transactions between PCI 2.2 and RapidIO. A mapping mechanism such as the AMT function described earlier is necessary to assign the proper transaction type based on the address space for which the transaction is targeted.

PCI 2.2 memory transactions do not specify a size. It is possible for a PCI master to read a continuous stream of data from a target or to write a continuous stream of data to a target. Because RapidIO is defined to have a maximum data payload of 256 bytes, PCI transactions that are longer than 256 bytes must be broken into multiple RapidIO operations. Table 9.2 shows the transaction mapping between PCI-X and RapidIO.

Table 9.1. PCI 2.2 to RapidIO transaction mapping

PCI command	RapidIO transaction	Comment
Interrupt-acknowledge	NREAD
Special-cycle	NWRITE
I/O-read	NREAD
I/O-write	NWRITE_R
Memory-read, memory-read-line, memory-read-multiple	NREAD or IO_READ_HOME	The PCI memory read transactions can be represented by the NREAD operation. If the operation is targeted to hardware-maintained globally coherent memory address space then the I/O Read operation must be used
Memory-write, memory-write-and-invalidate	NWRITE, NWRITE_R, or FLUSH	The PCI Memory Write and Memory-Write-and-Invalidate can be represented by the NWRITE operation. If reliable delivery of an individual ...