RapidIO: The Next Generation Communication Fabric For Embedded Application

1.6. RAPIDIO: A NEW APPROACH

The RapidIO interconnect architecture is an open standard which addresses the needs of a wide variety of embedded infrastructure applications. Applications include interconnecting microprocessors, memory, and memory mapped I/O devices in networking equipment, storage subsystems, and general purpose computing platforms.

This interconnect is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications with performance levels ranging from 1 to 60 Gbit/s performance levels.

Two families of RapidIO interconnects are defined: a parallel interface for high-performance microprocessor and system connectivity and a serial interface for serial backplane, DSP and associated serial control plane applications. The serial and parallel forms of RapidIO share the same programming models, transactions, and addressing mechanisms.

Supported programming models include basic memory mapped IO transactions; port-based message passing and globally shared distributed memory with hardware-based coherency. RapidIO also offers very robust error detection and provides a well-defined hardware and software-based architecture for recovering from and reporting transmission errors.

The RapidIO interconnect is defined as a layered architecture which allows scalability and future enhancements while maintaining backward compatibility.

1.6.1. Why RapidIO?

RapidIO is categorized as an intra-system interconnect as shown in Figure 1.5. Specifically, ...