RapidIO: The Next Generation Communication Fabric For Embedded Application

1.1. PROCESSOR PERFORMANCE AND BANDWIDTH GROWTH

Figure 1.1 shows the exponential growth of processor performance over the last 30 years. It also depicts the slower growth of processor bus frequency over that same period of time. The MHz scale of the chart is logarithmic and the difference between the core CPU performance, represented by the clock frequency, and the available bandwidth to the CPU, represented by the bus frequency, continues to grow. The use of cache memory and more advanced processor microarchitectures has helped to reduce this growing gap between CPU performance and available bus bandwidth. Increasingly processors are being developed with large integrated cache memories and directly integrated memory controllers. However multiple levels of on- and off-chip cache memory and directly integrated memory controllers, while useful for reducing the gap between a processor's data demands and the ability of its buses to provide the data, does little to support the connection of the processor to external peripheral devices or the connection of multiple processors together in multiprocessing (MP) systems.

Figure 1.1. Frequency and bandwidth growth

In addition to the increasing performance of processors, the need for higher levels of bus performance is also driven by two other key factors. First, the need for higher raw data bandwidth to support higher peripheral device ...