RapidIO: The Next Generation Communication Fabric For Embedded Application

2.14. PERFORMANCE

One of RapidIO's intended uses is as a processor and memory interface where both latency and bandwidth are important considerations. RapidIO may also be used to carry data streams where deterministic delivery behavior is required. RapidIO offers several features aimed at improving system performance. The high-speed nature of the interface allows it to offer bandwidth equivalent to or higher than that available from existing buses. The parallel physical layer uses separate clock and frame signals to reduce clock and packet delimitation overhead. Source routing and transaction priority tagging reduce the blocking of packets, especially those of a critical nature. Large data payloads of up to 256 bytes and responseless stream write operations move larger volumes of data with less transaction overhead while not blocking links for extreme periods of time.

2.14.1. Packet Structures

The RapidIO packet is structured to promote simplified construction and parsing of packets within a wider on-chip parallel interface. This then limits the amount of logic operating on the narrower high-frequency interface. Packets are organized in byte granularities with 32-bit word alignments. In this way RapidIO header fields will land consistently in specific byte lanes on the receiving device. This also limits the need for complex reassembly, lane steering and parsing logic.

2.14.2. Source Routing and Concurrency

Traditional bus-based systems, such as those using PCI, have relied on ...