RapidIO: The Next Generation Communication Fabric For Embedded Application

Appendix C. Parallel Physical Layer Registers

This appendix describes the command and status register (CSR) set that allows an external processing element to determine the capabilities, configuration, and status of a processing element using the parallel physical layer specification. This chapter describes only registers or register bits defined by this specification. Refer to the other RapidIO logical, transport, and physical specifications of interest to determine a complete list of registers and bit definitions. All registers are 32 bits and aligned to a 32-bit boundary.

These registers utilize the extended features blocks and can be accessed by maintenance operations. Any register offsets not defined are considered reserved for this specification unless otherwise stated. Read and write accesses to reserved register offsets will terminate normally and not cause an error condition in the target device. The extended features pointer (EF_PTR) contains the offset of the first extended features block in the extended features data structure for a device. The 8/16 LP-LVDS physical features block can exist in any position in the extended features data structure.

Table C.1 describes the required behavior for accesses to reserved register bits and reserved registers for the RapidIO Extended Features register space.

This appendix is divided into three sections, each addressing a different type of RapidIO device.