RapidIO: The Next Generation Communication Fabric For Embedded Application

15.5. LOW BUFFERING OVERHEAD

In the RapidIO protocol, all outstanding packets are buffered until the receiver positively acknowledges them. Since the maximum packet size is 276 bytes and the protocol allows up to 8 outstanding packets in the parallel specification and 32 outstanding packets in the serial specification, buffering can be implemented with the on-chip FPGA memory.

FPGAs today offer large amount of on-chip memory. The required memory for a RapidIO end point design, including separate receive and transmit buffers, is typically only a small fraction of overall memory resources available on an FPGA. For example, mid-range FPGA device densities will offer on the order of 1–3 Mb of memory. For a RapidIO implementation that uses separate transmit and receive buffers and can hold eight packets for each direction would require about 36 kb of memory. Even with segmented buffering to allow more efficient addressing of the on-chip memory and less complexity in the data path resources, the overall percentage of required memory for a RapidIO endpoint is still quite small. For implementations that may have several ports, the option to go to higher-density devices with even more on-chip memory is also available.