RapidIO: The Next Generation Communication Fabric For Embedded Application

15.6. EFFICIENT ERROR COVERAGE

With the built-in packet and control symbol error coverage, the protocol is able to offer hardware-based error recovery. Hardware-based error recovery allows systems to have higher reliability and lower system latency because packets can be checked for errors during each link transfer and immediately negatively acknowledged if necessary.

Data packets are covered by a 16-bit CRC that is embedded in the packet. Since the RapidIO protocol limits the maximum packet size to 276 bytes, a 16-bit CRC is sufficient to detect errors. Similar protocols utilize larger CRC polynomials to cover the data, even though the traffic may not utilize the maximum packet size allowed by those protocols. Larger packet size requirements on a protocol increase the size and complexity of the CRC logic to support protecting and checking the packet without necessarily being beneficial to the system requirements. With a 16-bit CRC, an FPGA implementation can implement the CRC function with less logic overhead and data path muxing.

In addition to data packets, RapidIO also defines an efficient mechanism to protect control symbols. In the parallel implementation, control symbols are transmitted with their complement to provide error coverage. In the serial implementation, control symbols are covered by a 5-bit CRC appended to the end of the control symbol.

All three error coverage mechanisms are simple and compact, allowing for reduced logic gate count to support them. These three ...