RapidIO: The Next Generation Communication Fabric For Embedded Application

A.3. COMMAND AND STATUS REGISTERS (CSRs)

All RapidIO end points or switches contain a set of command and status registers (CSRs) that allow an external device to control and determine the status of a target device's internal hardware. All registers are 32 bits wide and are organized and accessed in the same way as the CARs.

A.3.1. Mailbox CSR (Offset 0×40 Word 0)

The mailbox command and status register is accessed if an external processing element wishes to determine the status of this processing elements's mailbox hardware, if any is present; see Table A.12. It is not necessary to examine this register before sending a message since the RapidIO protocol shall accept, retry, or send an error response message, depending upon the status of the addressed mailbox. This register is read-only.

A.3.2. Write-port or Doorbell CSR (Offset 0×40 Word 1)

The write-port CSR is accessed if an external processing element wishes to determine the status of this processing element's write-port hardware; see Table A.13. It is not necessary to examine this register before sending a port-write transaction since the protocol will behave appropriately, depending upon the status of the hardware. This register is read-only.

Table A.12. Bit settings for mailbox CSR

Bit	Field name	Description
0	Mailbox 0 available	Mailbox 0 is initialized and ready to accept messages. If not available, all incoming message transactions return error responses
1	Mailbox 0 full	Mailbox 0 is full. All incoming message transactions ...