RapidIO: The Next Generation Communication Fabric For Embedded Application

9.1. ADDRESS MAP CONSIDERATIONS

PCI defines three physical address spaces, specifically, the memory, I/O memory, and con-figuration spaces. RapidIO, on the other hand, supports only memory and configuration spaces. I/O memory spaces are treated as memory spaces in RapidIO. Figure 9.2 shows a simple example of the PCI memory and I/O address spaces for a host bus segment. In order for devices on the PCI bus to communicate with other devices connected through RapidIO, it is necessary to provide a memory mapping function. The example PCI host memory map uses a 32-bit physical address space resulting in 4 Gbyte total address space. Host memory is shown at the bottom of the address map and peripheral devices at the top. The example shows two RapidIO bridge address windows. One window is located in the memory space and one window is located in the I/O space.

From the PCI side, any transactions issued to the bus segment with an address that matches the RapidIO bridge window will be captured by the RapidIO to PCI bridge for forwarding. Once the transaction has been accepted by the RapidIO to PCI bridge it must be translated to the proper RapidIO context, as shown in Figure 9.3. For the purposes of this discussion this function is called the address mapping and translation function (AMT). The AMT function is responsible for translating PCI addresses to RapidIO addresses. It is also responsible for the translation and assignment of the respective PCI and RapidIO transaction types. The address ...