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Programming the Cell Processor: For Games, Graphics, and Computation

Book Description

Make the Most of IBM’s Breakthrough Cell Processor in Any Gaming, Graphics, or Scientific Application

IBM’s Cell processor delivers truly stunning computational power: enough to satisfy even the most demanding gamers and graphics developers. That’s why Sony chose the Cell to drive its breakthrough PlayStation 3 and why Cell processors are at the heart of today’s most powerful supercomputers. But many developers have struggled to create high-performance Cell applications: the practical, coherent information they need simply hasn’t existed.

Programming the Cell Processor solves that problem once and for all. Whether you’re a game developer, graphics programmer, or engineer, Matthew Scarpino shows you how to create applications that leverage all the Cell’s extraordinary power. Scarpino covers everything from the Cell’s advanced architecture to its powerful tools and libraries, presenting realistic code examples that help you gain an increasingly deep and intuitive understanding of Cell development.

Scarpino illuminates each of the Cell’s most important technical innovations, introduces the commands needed to access its power, and walks you through the entire development process, including compiling, linking, debugging, and simulating code. He also offers start-to-finish case studies for three especially important Cell applications: games, graphics, and scientific computing. The Cell platform offers unprecedented potential, and this book will help you make the most of it.

  • Mastering the Cell SDK, including the GCC-based buildchain, ppu-gdb/spu-gdb debuggers, IBM Full System Simulator, and Cell IDE

  • Understanding the Cell’s central processing core, the PowerPC Processor Unit (PPU): structure, programming libraries, and AltiVec instructions

  • Programming the Synergistic Processor Unit (SPU): vector processing, communication, caching, assembler coding, and more

  • Leveraging SDK vector and matrix libraries, including the Large Matrix Library, BLAS Library, FFT libraries, Multiprecision Library, and Monte Carlo API

  • Coding basic 2D graphics using the Linux frame buffer

  • Building 3D graphics with the new Gallium OpenGL library 

  • Constructing 3D games with Ogre3D and packaging them using Collada digital content interchange

  • Optimizing the performance of your Cell applications

  • Developing on standard PCs and transferring code to Cell systems such as the PlayStation 3

  • Foreword xv

    Preface xvii

    Chapter 1: Introducing the Cell Processor 1

    Part I: The Software Development Tools 13

    Chapter 2: The Cell Software Development Kit (SDK) 15

    Chapter 3: Building Applications for the Cell Processor 35

    Chapter 4: Debugging and Simulating Applications 53

    Chapter 5: The Cell SDK Integrated Development Environment 83

    Part II: The PowerPC Processor Element (PPE) 97

    Chapter 6: Introducing the PowerPC Processor Unit (PPU) 99

    Chapter 7: The SPE Runtime Management Library (libspe) 125

    Chapter 8: SIMD Programming on the PPU, Part 1: Vector Libraries and Functions 153

    Chapter 9: SIMD Programming on the PPU, Part 2: Methods and Algorithms 195

    Part III: The Synergistic Processor Element (SPE) 217

    Chapter 10: Introducing the Synergistic Processor Unit (SPU) 219

    Chapter 11: SIMD Programming on the SPU 239

    Chapter 12: SPU Communication, Part 1: Direct Memory Access (DMA) 285

    Chapter 13: SPU Communication, Part 2: Events, Signals, and Mailboxes 317

    Chapter 14: Advanced SPU Topics: Overlays, Software Caching, and SPU Isolation 345

    Chapter 15: SPU Assembly Language 367

    Part IV: Mathematics and Computation 409

    Chapter 16: Vectors and Matrices 411

    Chapter 17: The Fast Fourier Transform (FFT) 439

    Chapter 18: Multiprecision Processing and Monte Carlo Methods 463

    Part V: Graphics and Games 489

    Chapter 19: Programming the Frame Buffer: Linux and the PlayStation 3 491

    Chapter 20: OpenGL on the Cell: Gallium and Mesa 503

    Chapter 21: Building Games with Ogre3D 529

    Chapter 22: Packaging Graphics with COLLADA 559

    Epilogue 581

    Part VI: Appendices 583

    Appendix A: Understanding ELF Files 585

    Appendix B: Updating the PS3 Add-On Packages and Installing a New Linux Kernel 609

    Appendix C: The Accelerated Library Framework (ALF) 617

    Appendix D: SPU Instruction Set Reference 649

    Appendix E: A Brief Introduction to Tcl 661

    Index 669

    Table of Contents

    1. Copyright
      1. Dedication
    2. Foreword
    3. Preface
    4. Acknowledgments
    5. About the Author
    6. 1. Introducing the Cell Processor
      1. 1.1. Background of the Cell Processor
        1. History of the Cell
        2. Potential of the Cell Processor for Scientific Computing
      2. 1.2. The Cell Architecture: An Overview
        1. The Memory Interface Controller (MIC)
        2. The PowerPC Processor Element (PPE)
        3. The Synergistic Processor Element (SPE)
        4. The Element Interconnect Bus (EIB)
        5. The Input/Output Interface (IOIF)
      3. 1.3. The Cell Broadband Engine Software Development Kit (SDK)
      4. 1.4. Conclusion
    7. I. The Software Development Tools
      1. 2. The Cell Software Development Kit (SDK)
        1. 2.1. Installing Fedora Core on the PlayStation 3
          1. Obtaining the Fedora Core Image for the Cell Processor
          2. Obtaining the Bootloader for Linux/PS3
          3. Installing Linux onto the PS3
        2. 2.2. Installing the Cell Software Development Kit
          1. Downloading the Cell SDK Files
          2. Preparing for SDK Installation
          3. Understanding and Executing the cellsdk Script
          4. Optional SDK Packages
        3. 2.3. SDK Software Licensing
          1. IBM’s International License Agreement for Early Release of Programs (ILAR)
          2. GNU General Public License (GPL)
          3. Lesser GNU General Public License (LGPL)
        4. 2.4. Exploring the SDK Installation
          1. SDK on a Cell System
            1. Executables in /usr/bin
            2. Additional Tools in /opt/cell/sdk
          2. SDK on an x86 System
            1. Executables and Libraries in /opt/cell/toolchain
            2. Simulator Files in /opt/ibm/systemsim-cell
        5. 2.5. Connecting to a Remote Cell Processor System
          1. Send Commands to the Cell System with PuTTY
          2. Transfer Files to the Cell System with WinSCP
        6. 2.6. Conclusion
      2. 3. Building Applications for the Cell Processor
        1. 3.1. Software Development for the Cell Processor
          1. Building Applications for the PowerPC Processor Unit (PPU)
            1. The PPU Preprocessor, ppu-cpp
            2. The PPU Compiler, ppu-gcc
            3. The PPU Assembler, ppu-as
            4. The PPU Linker, ppu-ld
          2. The Short Way: Building PPU Applications with ppu-gcc
          3. Building Applications for the Synergistic Processor Unit (SPU)
        2. 3.2. Make and Makefiles
          1. Anatomy of a Makefile
            1. Makefile Dependency Lines
            2. Shell Lines
            3. Makefile Variables and Comments
            4. A Simple Makefile Example
          2. Advanced Makefile Development
            1. Phony Targets
            2. Automatic Variables
            3. Pattern Rules and Built-In Rules
            4. An Advanced Makefile
        3. 3.3. Conclusion
      3. 4. Debugging and Simulating Applications
        1. 4.1. Debugging Cell Applications
          1. Debugging SPU Applications with spu-gdb
            1. Breakpoints and Watchpoints
            2. Reading Processor Information
            3. Controlling Application Execution
            4. An Example Debug Session
        2. 4.2. The IBM Full-System Simulator for the Cell Broadband Engine (SystemSim)
          1. SystemSim Configuration
          2. Starting and Running SystemSim
            1. The SystemSim Command Window
            2. The SystemSim Console Window
          3. Compiling and Running Simulated Applications
            1. Building the Example Application
            2. Transferring the Application to the Simulated Cell
            3. Running the Application
          4. SPU Statistics and Checkpoints
            1. SPU Statistics and Profiling Commands
            2. SPU Checkpoints
          5. SystemSim Trigger Events and Trigger Actions
            1. Trigger Events
            2. Trigger Actions
            3. Associating Trigger Actions with Trigger Events
          6. SystemSim Emitters
            1. Emitter Event Configuration
            2. Coding Emitter Readers Pt 1: EMIT_DATA
            3. Coding Emitter Readers Pt 2: The Emitter API
        3. 4.3. Conclusion
      4. 5. The Cell SDK Integrated Development Environment
        1. 5.1. Eclipse and the C/C++ Development Tooling
          1. Installing Eclipse
          2. Installing the CDT
          3. Installing the Cell IDE
        2. 5.2. Managing an SPU Project with the Cell IDE
          1. Creating a Cell Project
          2. Adding and Editing Source Code
          3. Project Configuration
          4. Building Projects with the Cell IDE
        3. 5.3. Running Executables with the Cell IDE
          1. Running Executables on a Remote Cell System
          2. Running Executables on a Cell Simulator
          3. Debugging Executables with the Cell IDE
        4. 5.4. Conclusion
    8. II. The PowerPC Processor Element (PPE)
      1. 6. Introducing the PowerPC Processor Unit (PPU)
        1. 6.1. Programming the PowerPC Processor Unit
          1. PPU Datatypes
          2. PPU Bit Ordering
          3. PPU Libraries
          4. PPU Intrinsics
          5. PPU Timing and the Time Base Register
        2. 6.2. The PPU: A Bird’s-Eye View
          1. The PPU and the PowerPC
          2. The PPU’s Functional Units
          3. The PPU’s Register File
        3. 6.3. PPU Instruction Processing
          1. 1. Instruction Cache (Four Stages)
          2. 2. Branch Prediction (Four Stages)
          3. 3. Instruction Buffer (Two Stages) and Dispatch
          4. 4. Microcode Translation (11 Stages)
          5. 5. Decode (Three Stages)
          6. 6. Issue (Three Stages)
        4. 6.4. Configuring the Pipeline
          1. Controlling the Instruction Cache
          2. Preventing Branch Misses
          3. Removing Microcoded Instructions
          4. Improving Chances of Dual Issue
        5. 6.5. PPU Dual-Threaded Operation
          1. PPU Multithreading Example
          2. PPU Intrinsics for Dual-Threaded Applications
        6. 6.6. PPU Memory Access: The Load Store Unit (LSU)
          1. The Data Cache (DCache) and Memory Synchronization
          2. The PowerPC Processor Storage Subsystem (PPSS)
        7. 6.7. PPU Address Translation: The Memory Management Unit (MMU)
          1. Virtual Memory and Segments
          2. Pages and the Translation Lookaside Buffer (TLB)
          3. Preventing TLB Misses by Using Hugepages
        8. 6.8. Conclusion
      2. 7. The SPE Runtime Management Library (libspe)
        1. 7.1. The Big Picture
          1. A Basic Example of the SPE Runtime Management Library
            1. Building the Application from the Command Line
            2. Building the Application with the Cell SDK IDE
        2. 7.2. The SPE Management Process
          1. 1. Examine System Configuration (Optional)
          2. 2. Embed the SPE Executable into the PPU Application
            1. Compile-Time Embedding
            2. Runtime Embedding
          3. 3. Create a Context for Each SPE
          4. 4. Create an Event Handler and Register Events (Optional)
          5. 5. Load the Program Handle into the Context and Run the Executable
          6. 6. Wait for Events and Analyze Stop Information (Optional)
          7. 7. Deallocate Data Structures
        3. 7.3. Linux Pthreads and libspe
          1. Linux Pthreads
          2. IBM Code Conventions
        4. 7.4. Gang Contexts and Affinity
        5. 7.5. Direct SPE Access
          1. The SPU File System (SPUFS)
          2. Direct SPE Access in libspe
        6. 7.6. Conclusion
      3. 8. SIMD Programming on the PPU, Part 1: Vector Libraries and Functions
        1. 8.1. Introduction to Vectors and PPU Vector Processing
          1. PPU Vector Datatypes
          2. PPU Floating-Point Values: Graphics Rounding Mode and Java Mode
          3. PPU Vector Registers
        2. 8.2. Vector Function Libraries
          1. AltiVec
          2. SIMD Math
          3. MASSV
        3. 8.3. SIMD Functions for the PPU
          1. Load and Store Functions
          2. Addition/Subtraction Functions
          3. Multiplication/Division Functions
          4. Conversion, Packing, and Splatting Functions
          5. Permutation and Shifting Functions
          6. Basic Unary Instructions
          7. Logic Functions
          8. Vector Comparison, Part 1: Vector Return Value
          9. Vector Comparison, Part 2: Scalar Return Value
          10. Exponent/Logarithm Functions
          11. Trigonometric Functions
          12. Floating-Point Analysis Functions
        4. 8.4. Conclusion
      4. 9. SIMD Programming on the PPU, Part 2: Methods and Algorithms
        1. 9.1. From Scalars to Vectors
          1. Accessing Unaligned Memory and Unrolling Loops
            1. vec_perm and vec_lvsl
            2. Unaligned Vectorized Addition
          2. SOA Versus AOS
        2. 9.2. Vectorizing Data Transfer and String Manipulation
          1. libmotovec and libfreevec
          2. memcpy
          3. strcmp
        3. 9.3. Vectorized Insertion Sort
          1. Insertion Sort
          2. Intervector Sort
          3. Intravector Sort
        4. 9.4. Conclusion
    9. III. The Synergistic Processor Element (SPE)
      1. 10. Introducing the Synergistic Processor Unit (SPU)
        1. 10.1. The Synergistic Processor Unit
          1. SPU Functional Units
          2. SPU User Registers
        2. 10.2. SPU Datatypes and Floating-Point Processing
          1. SPU Scalar Datatypes
          2. SPU Vector Datatypes
          3. Floating-Point Processing on the SPU
        3. 10.3. SPU Libraries in the SDK
          1. C/C++ Standard Libraries on the SPU
          2. SPU Intrinsics and Additional Libraries
        4. 10.4. The SPU Local Store
          1. Memory Synchronization
        5. 10.5. SPU Initialization and Loading
          1. SPU Initialization and Stack Operation
          2. SPU Executable Loading and Spulets
        6. 10.6. SPU Dynamic Allocation and the Heap
        7. 10.7. The SPU Instruction Pipeline
          1. Prefetch and Buffering
          2. Branch Processing and Prediction
          3. Decode
          4. Issue
        8. 10.8. Conclusion
      2. 11. SIMD Programming on the SPU
        1. 11.1. SPU Vector Intrinsics Versus PPU Vector Intrinsics
          1. Similarities Between PPU and SPU SIMD Coding
          2. Differences Between PPU and SPU SIMD Coding
          3. Comparing the SPU and PPU Vector Functions
        2. 11.2. The SIMD Math and MASSV Libraries
          1. SIMD Math Library
          2. MASSV
        3. 11.3. The SPU Decrementer
        4. 11.4. SPU Vector Functions
          1. SPU Vector/Scalar Functions
          2. SPU Addition/Subtraction Functions
          3. SPU Multiplication/Division Functions
          4. SPU Shuffle/Select Functions
          5. SPU Compare/Count Functions
          6. SPU Shift/Rotate Functions
            1. SPU Rotation Functions
            2. SPU Shift-Right Functions
          7. SPU Basic Unary Functions
          8. SPU Logical Functions
          9. Exponent/Logarithm Functions
          10. Trigonometric Functions
          11. Floating-Point Analysis Functions
        5. 11.5. Common SPU Tasks
          1. Processing Unaligned Data
          2. Converting from AOS to SOA and Back
        6. 11.6. Accessing the SPU’s FPSCR
          1. Detecting Errors with the FPSCR
          2. Configuring the Double-Precision Rounding Mode with the FPSCR
        7. 11.7. Conclusion
      3. 12. SPU Communication, Part 1: Direct Memory Access (DMA)
        1. 12.1. The Element Interconnect Bus (EIB) and the Memory Flow Controller (MFC)
          1. The Element Interconnect Bus (EIB)
          2. The Memory Flow Controller (MFC)
            1. The Scholar-Butler Analogy
            2. External Access to the MFC
        2. 12.2. Introducing DMA
        3. 12.3. Tag Groups and DMA
          1. Checking for DMA Completion
            1. Checking the MFC Command Queue
          2. Ordering Transfers in a Tag Group
        4. 12.4. Multibuffered DMA
          1. Double Buffering
        5. 12.5. DMA Request Lists
          1. DMA List Elements
          2. DMA List Functions
        6. 12.6. SPU-SPU and SPU-SPU DMA Transfers
          1. PPU-Initiated DMA
          2. DMA Between SPUs
        7. 12.7. Atomic DMA and the Synchronization Library
          1. Atomic DMA Functions
          2. Synchronization Library
            1. Atomic Operations
            2. Mutexes
            3. Reader/Writer Locks
            4. Condition Variables
            5. Completion Variables
          3. The Cashier Problem
        8. 12.8. Conclusion
      4. 13. SPU Communication, Part 2: Events, Signals, Mailboxes
        1. 13.1. SPE Channels and the Memory Flow Controller
          1. The Scholar-Butler Analogy and Channels
          2. SPU Channels and Channel Functions
          3. PPU Access to MFC Registers
        2. 13.2. Events and Interrupts
          1. Step 1: Select Events of Interest
          2. Step 2: Recognize Events as They Occur
            1. Waiting
            2. Polling
            3. Interrupt Handling
          3. Step 3: Acknowledge Events
          4. PPE Event Handling
        3. 13.3. Mailboxes
          1. SPU Mailbox Communication
            1. Mailbox Write
            2. Mailbox Read
            3. Mailbox Event Processing
          2. PPU Mailbox Communication
          3. SPU-SPU Mailbox Communication
        4. 13.4. Signal Communication
          1. Signal Notification Channels and Read Operations
          2. Sending Signals from an SPE
          3. Signal Notification Modes and Many-to-One Communication
          4. PPU Signaling
          5. Signals and SPE Synchronization
        5. 13.5. Multiprocessor Synchronization
          1. Multiprocessor DMA Ordering
          2. MFC Multisource Synchronization
        6. 13.6. Conclusion
      5. 14. Advanced SPU Topics: Overlays, Software Caching, and SPU Isolation
        1. 14.1. SPU Overlays
          1. Overlays and the GNU Linker Script
          2. Overlay Code
        2. 14.2. SPU Software Cache
          1. Configuring the Cache
          2. Accessing the Cache
            1. Safe Software Cache Functions
            2. Unsafe Software Cache Functions
          3. Heapsort and the Software Cache
          4. Cache Statistics
        3. 14.3. SPU Security and Isolation
          1. SPU Security Tools
          2. Signing and Verifying SPU Executables
            1. Keys and Certificates
            2. Building Secure Applications
          3. Libspe and Secure Contexts
          4. Application Encryption
          5. The SPU Isolation Library
            1. Functions in the SPU Isolation Library
            2. Communicating with an Isolated SPU
        4. 14.4. Conclusion
      6. 15. SPU Assembly Language
        1. 15.1. Why Learn SPU Assembly?
        2. 15.2. Specific Intrinsics and Assembly-Coded Applications
          1. Specific Intrinsics
          2. Introducing the SPU Assembly Language
            1. Creating Sections in Assembly
            2. A Simple Assembly File
            3. Building an Assembly-Coded Application
            4. Debugging an Assembly-Coded Application
        3. 15.3. SPU Load and Store Instructions
          1. SPU Addressing Modes
          2. Load/Store Instructions
          3. Load Immediate Instructions
        4. 15.4. SPU Shuffle and Select Instructions
          1. Byte Shuffling and Shuffle Mask Creation
          2. Bit Selection and Selection Mask Creation
        5. 15.5. SPU Arithmetic and Logic Instructions
          1. SPU Addition and Subtraction Instructions
          2. SPU Multiplication Instructions
          3. SPU Logic Instructions
        6. 15.6. SPU Compare, Branch, and Halt Instructions
          1. SPU Compare Instructions
          2. SPU Branch Instructions
          3. SPU Hint-for-Branch Instructions
          4. SPU Halt Instructions
        7. 15.7. SPU Channel and Control Instructions
        8. 15.8. SPU Shift and Rotate Instructions
          1. SPU Shift Instructions
          2. SPU Rotate Instructions
        9. 15.9. SPU Counting and Conversion Instructions
        10. 15.10. Assembly Language and Function Calls
          1. Writing an Assembly-Coded Function
            1. Declaring the Function in Assembly
            2. Managing the Stack
            3. Assembly-Coded Function Example
          2. Calling C/C++ Functions from Assembly Code
        11. 15.11. Assembly and the SPU Dual-Pipeline Architecture
        12. 15.12. Conclusion
    10. IV. Mathematics and Computation
      1. 16. Vectors and Matrices
        1. 16.1. The Vector Library
          1. Vector Products and Lengths
          2. Graphic and Miscellaneous Vector Functions
        2. 16.2. The Matrix Library: 4x4 Matrices
          1. Basic Matrix Operations
          2. Projection Matrices
            1. Orthogonal Projection
            2. Perspective Projection
          3. Vector Rotation
            1. Rotating Coordinates in 2D and 3D
            2. Quaternions and the Matrix Library
        3. 16.3. The Large Matrix Library
          1. Basic Large Matrix Operations
          2. Linear Equation Solution
        4. 16.4. The Basic Linear Algebra Subprograms (BLAS) Library
        5. 16.5. Multiprocessor Matrix Multiplication
          1. Running the Application
          2. The PPU Creates the Matrix and SPU Contexts
          3. The SPUs Receive Information and Load Matrix Blocks
          4. The SPUs Process the Matrix Blocks and Store Results
        6. 16.6. Conclusion
      2. 17. The Fast Fourier Transform (FFT)
        1. 17.1. Introducing Frequency Analysis and the Discrete Fourier Transform
          1. The Time Domain and the Frequency Domain
          2. Signals and Sampling
          3. The Discrete Fourier Transform
            1. Frequencies of Interest
            2. The Single-Frequency Vector
            3. The DFT Equation
          4. A DFT Example
          5. DFT Computation and the FFT
        2. 17.2. Introducing the Fast Fourier Transform
          1. The Stretching Property
          2. The Shifting Property
          3. The Addition Property
          4. The Two- and Four-Point Fourier Transform
        3. 17.3. The Example FFT Library (libfft_example)
          1. The One-Dimensional FFT
          2. The Two-Dimensional FFT
        4. 17.4. The FFT Library (libfft and libfft_spu)
          1. The FFT Library for the PPU
          2. The FFT Library for the SPU
        5. 17.5. Conclusion
      3. 18. Multiprecision Processing and Monte Carlo Methods
        1. 18.1. Multiprecision Mathematics Library (libmpm)
          1. Multiprecision General Arithmetic/Logic Functions
          2. Multiprecision Division and Modular Operations
            1. Modular Exponentiation
          3. Public Key Cryptography and RSA
        2. 18.2. The Monte Carlo Library (libmc_rand)
          1. Generating Pseudo- and Quasi-Random Numbers
            1. Feedback Shift Registers (FSRs) and Pseudo-Random Numbers
            2. Quasi-Random Numbers and the Sobol Generator
          2. Transforming the Distribution of Number Sequences
            1. The Monte Carlo Transformation Methods
            2. The Monte Carlo Transformation Functions
        3. 18.3. Conclusion
    11. V. Graphics and Games
      1. 19. Programming the Frame Buffer: Linux and the PlayStation 3
        1. 19.1. Graphical Displays, Linux Devices, and the Frame Buffer
          1. Display Monitors and Linux Configuration
            1. Display Speed and Frame Rate
          2. Linux Devices and the Frame Buffer
            1. Character and Block Devices
            2. The Linux Frame Buffer
        2. 19.2. I/O Control (ioctl) Instructions
          1. Linux Frame Buffer I/O Control
          2. PlayStation 3 Frame Buffer I/O Control
        3. 19.3. Drawing the Frame Buffer
        4. 19.4. Conclusion
      2. 20. OpenGL on the Cell: Gallium and Mesa
        1. 20.1. OpenGL, Mesa, and Gallium
          1. OpenGL: Past, Present, and Future
            1. Architecture Review Board, Extensions, and Difficulties
            2. The Khronos Group and OpenGL 3.0
          2. Mesa
          3. Gallium
        2. 20.2. Acquiring and Building Mesa/Gallium
          1. Downloading the Mesa/Gallium Source Code
          2. Building the Mesa/Gallium Libraries
        3. 20.3. The OpenGL Utility Toolkit (GLUT)
          1. Creating Windows with GLUT
        4. 20.4. A Gentle Introduction to OpenGL, Part 1: Creating the Viewing Region
          1. OpenGL Datatypes
          2. Defining the OpenGL Viewing Region
            1. Orthographic Projections in 2D and 3D
            2. Perspective Projections
            3. Example Perspective Projection
        5. 20.5. A Gentle Introduction to OpenGL, Part 2: Vertices, Colors, Normals, and Vertex Buffer Objects
          1. OpenGL Vertices and Shapes
          2. Defining Vertex Color
          3. OpenGL Normal Vectors
          4. OpenGL Vertex Buffer Objects
        6. 20.6. Conclusion
      3. 21. Building Games with Ogre3D
        1. 21.1. Introducing Ogre
          1. Downloading and Building the Ogre Libraries
            1. Installing FreeImage
            2. Installing Ogre
          2. Building an Ogre Application
        2. 21.2. The Basics of Ogre Development
          1. The Root and Ogre Plug-ins
            1. Ogre Plug-ins
            2. The Root Class
          2. The SceneManager and the Camera
          3. The Viewport
        3. 21.3. Ogre Resources: Meshes, Skeletons, and Materials
          1. Ogre Meshes
          2. Ogre Skeletons
          3. Ogre Materials
          4. Accessing Resources in Applications
        4. 21.4. Managing the Scene: Entities, Nodes, and Lighting
          1. Meshes and Entities
          2. Nodes and the SceneManager
          3. Adding Lights to the Scene
        5. 21.5. Moving the Ninja: User Input, Animation, and Frame Listening
          1. Responding to User Input
          2. Animation
          3. The FrameListener
        6. 21.6. Conclusion
      4. 22. Packaging Graphics with COLLADA
        1. 22.1. Introducing COLLADA
        2. 22.2. COLLADA’s Digital Asset Exchange (DAE) Format
          1. The <asset> Element
          2. The <library_geometries> Element
            1. The <source> Subelement
            2. The <vertices> Subelement
            3. COLLADA Shapes
          3. The <library_controllers> Element
            1. The <skin> Subelement
            2. The <morph> Subelement
          4. The <library_materials> Element
            1. The <technique_hint> Subelement
            2. The <setparam> Subelement
        3. 22.3. The COLLADA Application Programming Interface (API)
          1. Installing the COLLADA Libraries
          2. Basic Objects of the COLLADA API
            1. The DAE Class
          3. The Runtime Database and the DAE Elements
          4. The COLLADA Document Object Model (DOM)
        4. 22.4. Conclusion
      5. Epilogue
    12. VI. Appendices
      1. A. Understanding ELF Files
        1. A.1. ELF Object Files
          1. The ELF Header
          2. The Section Headers
          3. Symbol and String Tables
          4. Relocation Tables
        2. A.2. ELF Executable Files
          1. Dynamic Linking
        3. A.3. ELF Libraries
          1. Static Libraries
          2. Shared Libraries
        4. A.4. SPU-ELF and CESOF Files
          1. SPU-ELF Files and the TOE Section
          2. The CESOF Format
          3. Creating the Complete PPU Executable
        5. A.5. Accessing ELF Files in Code
        6. A.6. Conclusion
      2. B. Updating the PS3 Add-On Packages and Installing a New Linux Kernel
        1. B.1. Add-On Packages for the PlayStation 3
          1. The PS3 Add-On Packages
          2. Installing the PS3 Add-On Packages
        2. B.2. Configuring and Installing a New Linux Kernel
          1. Accessing the Kernel Source Code
          2. Configuring and Building the Linux Kernel
          3. Configuring the PS3 to Boot the New Kernel
      3. C. The Accelerated Library Framework (ALF)
        1. C.1. Introduction to ALF
          1. libspe and ALF
          2. Accelerator Memory Buffers
        2. C.2. ALF Applications on the Host (PPU)
          1. Initializing the ALF Environment
            1. alf_init
              1. alf_query_system_info
              2. alf_num_instances_set
          2. Task Descriptors
            1. Customizing the Task Descriptor
            2. Adding a Task Context to the Task Descriptor
          3. Creating Tasks
          4. ALF Work Blocks
            1. Creating Work Blocks
            2. Adding Parameter Contexts to a Work Block
            3. Work Blocks and Data Transfer Lists
            4. Adding the Work Block to the Task
          5. Launching and Ending the Task
        3. C.3. ALF Applications on the Accelerator (SPU)
          1. The Five ALF Accelerator Stages
          2. Implementing ALF Accelerator Stages with Functions
            1. Stage 1: Setup Task Context
            2. Stage 2: Create Input Data Transfer Lists
            3. Stage 3: Process Computational Kernel
            4. Stage 4: Create Output Data Transfer Lists
            5. Stage 5: Merge Task Context
          3. Kernel API Export Definition Section
          4. Accelerator Environment Functions
        4. C.4. ALF Example Applications
          1. ALF Example 1: Text Transfer and Display
          2. ALF Example 2: Matrix Addition and Subtraction
            1. Partitioning Data on the Host
            2. Partitioning Data on the Accelerator
        5. C.5. ALF Task Dependency and Event Processing
          1. ALF Task Dependency
          2. ALF Events
        6. C.6. Conclusion
      4. D. SPU Instruction Set Reference
      5. E. A Brief Introduction to Tcl
        1. E.1. Introducing Tcl
        2. E.2. Higher-Level Tcl
          1. Tcl Conditional Statement: if...elseif...else
          2. Tcl List Processing
          3. Tcl Arrays
          4. Loop Iteration: for and foreach
        3. E.3. Procedure Declarations
        4. E.4. Conclusion