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Principles of Power Integrity for PDN Design—Simplified

Book Description

Consistently Design PDNs That Deliver Reliable Performance at the Right Cost

Too often, PDN designs work inconsistently, and techniques that work in some scenarios seem to fail inexplicably in others. This book explains why and presents realistic processes for getting PDN designs right in any new product. Drawing on 60+ years of signal and power integrity experience, Larry Smith and Eric Bogatin show how to manage noise and electrical performance, and complement intuition with analysis to balance cost, performance, risk, and schedule. Throughout, they distill the essence of complex real-world problems, quantify core principles via approximation, and apply them to specific examples. For easy usage, dozens of key concepts and observations are highlighted as tips and listed in quick, chapter-ending summaries.

Coverage includes
• A practical, start-to-finish approach to consistently meeting PDN performance goals
• Understanding how signals interact with interconnects
• Identifying root causes of common problems, so you can avoid them
• Leveraging analysis tools to efficiently explore design space and optimize tradeoffs
• Analyzing impedance-related properties of series and parallel RLC circuits
• Measuring low impedance for components and entire PDN ecologies
• Predicting loop inductance from physical design features
• Reducing peak impedances from combinations of capacitors
• Understanding power and ground plane properties in the PDN interconnect
• Taming signal integrity problems when signals change return planes
• Reducing peak impedance created by on-die capacitance and package lead inductance
• Controlling transient current waveform interactions with PDN features
• Simple spreadsheet-based analysis techniques for quickly creating first-pass designs

This guide will be indispensable for all engineers involved in PDN design, including product, board, and chip designers; system, hardware, component, and package engineers; power supply designers, SI and EMI engineers, sales engineers, and their managers.

Table of Contents

  1. About This E-Book
  2. Title Page
  3. Copyright Page
  4. Contents at a glance
  5. Contents
  6. Preface
  7. Acknowledgments
  8. About the Authors
  9. Chapter 1 Engineering the Power Delivery Network
    1. 1.1   What Is the Power Delivery Network (PDN) and Why Should I Care?
    2. 1.2   Engineering the PDN
    3. 1.3   “Working” or “Robust” PDN Design
    4. 1.4   Sculpting the PDN Impedance Profile
    5. 1.5   The Bottom Line
    6. Reference
  10. Chapter 2 Essential Principles of Impedance for PDN Design
    1. 2.1   Why Do We Care About Impedance?
    2. 2.2   Impedance in the Frequency Domain
    3. 2.3   Calculating or Simulating Impedance
    4. 2.4   Real Circuit Components vs. Ideal Circuit Elements
    5. 2.5   The Series RLC Circuit
    6. 2.6   The Parallel RLC Circuit
    7. 2.7   The Resonant Properties of a Series and Parallel RLC Circuit
    8. 2.8   Examples of RLC Circuits and Real Capacitors
    9. 2.9   The PDN as Viewed by the Chip or by the Board
    10. 2.10 Transient Response
    11. 2.11 Advanced Topic: The Impedance Matrix
    12. 2.12 The Bottom Line
    13. References
  11. Chapter 3 Measuring Low Impedance
    1. 3.1   Why Do We Care About Measuring Low Impedance?
    2. 3.2   Measurements Based on the V/I Definition of Impedance
    3. 3.3   Measuring Impedance Based on the Reflection of Signals
    4. 3.4   Measuring Impedance with a VNA
    5. 3.5   Example: Measuring the Impedance of Two Leads in a DIP
    6. 3.6   Example: Measuring the Impedance of a Small Wire Loop
    7. 3.7   Limitations of VNA Impedance Measurements at Low Frequency
    8. 3.8   The Four-Point Kelvin Resistance Measurement Technique
    9. 3.9   The Two-Port Low Impedance Measurement Technique
    10. 3.10 Example: Measuring the Impedance of a 1-inch Diameter Copper Loop
    11. 3.11 Accounting for Fixture Artifacts
    12. 3.12 Example: Measured Inductance of a Via
    13. 3.13 Example: Small MLCC Capacitor on a Board
    14. 3.14 Advanced Topic: Measuring On-Die Capacitance
    15. 3.15 The Bottom Line
    16. References
  12. Chapter 4 Inductance and PDN Design
    1. 4.1   Why Do We Care About Inductance in PDN Design?
    2. 4.2   A Brief Review of Capacitance to Put Inductance in Perspective
    3. 4.3   What Is Inductance? Essential Principles of Magnetic Fields and Inductance
    4. 4.4   Impedance of an Inductor
    5. 4.5   The Quasi-Static Approximation for Inductance
    6. 4.6   Magnetic Field Density, B
    7. 4.7   Inductance and Energy in the Magnetic Field
    8. 4.8   Maxwell’s Equations and Loop Inductance
    9. 4.9   Internal and External Inductance and Skin Depth
    10. 4.10 Loop and Partial, Self- and Mutual Inductance
    11. 4.11 Uniform Round Conductors
    12. 4.12 Approximations for the Loop Inductance of Round Loops
    13. 4.13 Loop Inductance of Wide Conductors Close Together
    14. 4.14 Approximations for the Loop Inductance of Any Uniform Transmission Line
    15. 4.15 A Simple Rule of Thumb for Loop Inductance
    16. 4.16 Advanced Topic: Extracting Loop Inductance from the S-parameters Calculated with a 3D Field Solver
    17. 4.17 The Bottom Line
    18. References
  13. Chapter 5 Practical Multi-Layer Ceramic Chip Capacitor Integration
    1. 5.1   Why Use Capacitors?
    2. 5.2   Equivalent Circuit Models for Real Capacitors
    3. 5.3   Combining Multiple Identical Capacitors in Parallel
    4. 5.4   The Parallel Resonance Frequency Between Two Different Capacitors
    5. 5.5   The Peak Impedance at the PRF
    6. 5.6   Engineering the Capacitance of a Capacitor
    7. 5.7   Capacitor Temperature and Voltage Stability
    8. 5.8   How Much Capacitance Is Enough?
    9. 5.9   The ESR of Real Capacitors: First- and Second-Order Models
    10. 5.10 Estimating the ESR of Capacitors from Spec Sheets
    11. 5.11 Controlled ESR Capacitors
    12. 5.12 Mounting Inductance of a Capacitor
    13. 5.13 Using Vendor-Supplied S-parameter Capacitor Models
    14. 5.14 How to Analyze Vendor-Supplied S-Parameter Models
    15. 5.15 Advanced Topics: A Higher Bandwidth Capacitor Model
    16. 5.16 The Bottom Line
    17. References
  14. Chapter 6 Properties of Planes and Capacitors
    1. 6.1   The Key Role of Planes
    2. 6.2   Low-Frequency Property of Planes: Parallel Plate Capacitance
    3. 6.3   Low-Frequency Property of Planes: Fringe Field Capacitance
    4. 6.4   Low-Frequency Property of Planes: Fringe Field Capacitance in Power Puddles
    5. 6.5   Loop Inductance of Long, Narrow Cavities
    6. 6.6   Spreading Inductance in Wide Cavities
    7. 6.7   Extracting Spreading Inductance from a 3D Field Solver
    8. 6.8   Lumped-Circuit Series and Parallel Self-Resonant Frequency
    9. 6.9   Exploring the Features of the Series LC Resonance
    10. 6.10 Spreading Inductance and Source Contact Location
    11. 6.11 Spreading Inductance Between Two Contact Points
    12. 6.12 The Interactions of a Capacitor and Cavities
    13. 6.13 The Role of Spreading Inductance: When Does Capacitor Location Matter?
    14. 6.14 Saturating the Spreading Inductance
    15. 6.15 Cavity Modal Resonances and Transmission Line Properties
    16. 6.16 Input Impedance of a Transmission Line and Modal Resonances
    17. 6.17 Modal Resonances and Attenuation
    18. 6.18 Cavity Modes in Two Dimensions
    19. 6.19 Advanced Topic: Using Transfer Impedance to Probe Spreading Inductance
    20. 6.20 The Bottom Line
    21. References
  15. Chapter 7 Taming Signal Integrity Problems When Signals Change Return Planes
    1. 7.1   Signal Integrity and Planes
    2. 7.2   Why the Peak Impedances Matter
    3. 7.3   Reducing Cavity Noise through Lower Impedance and Higher Damping
    4. 7.4   Suppressing Cavity Resonances with Shorting Vias
    5. 7.5   Suppressing Cavity Resonances with Many DC Blocking Capacitors
    6. 7.6   Estimating the Number of DC Blocking Capacitors to Suppress Cavity Resonances
    7. 7.7   Determining How Many DC Blocking Capacitors Are Needed to Carry Return Current
    8. 7.8   Cavity Impedance with a Suboptimal Number of DC Blocking Capacitors
    9. 7.9   Spreading Inductance and Capacitor Mounting Inductance
    10. 7.10 Using Damping to Suppress Parallel Resonant Peaks Created by a Few Capacitors
    11. 7.11 Cavity Losses and Impedance Peak Reduction
    12. 7.12 Using Multiple Capacitor Values to Suppress Impedance Peak
    13. 7.13 Using Controlled ESR Capacitors to Reduce Peak Impedance Heights
    14. 7.14 Summary of the Most Important Design Principles for Managing Return Planes
    15. 7.15 Advanced Topic: Modeling Planes with Transmission Line Circuits
    16. 7.16 The Bottom Line
    17. References
  16. Chapter 8 The PDN Ecology
    1. 8.1   Putting the Elements Together: The PDN Ecology and the Frequency Domain
    2. 8.2   At the High-Frequency End: The On-Die Decoupling Capacitance
    3. 8.3   The Package PDN
    4. 8.4   The Bandini Mountain
    5. 8.5   Estimating the Typical Bandini Mountain Frequency
    6. 8.6   Intrinsic Damping of the Bandini Mountain
    7. 8.7   The Power Ground Planes with Multiple Via Pair Contacts
    8. 8.8   Looking from the Chip Through the Package into the PCB Cavity
    9. 8.9   Role of the Cavity: Small Boards, Large Boards, and “Power Puddles”
    10. 8.10 At the Low Frequency: The VRM and Its Bulk Capacitor
    11. 8.11 Bulk Capacitors: How Much Capacitance Is Enough?
    12. 8.12 Optimizing the Bulk Capacitor and VRM
    13. 8.13 Building the PDN Ecosystem: The VRM, Bulk Capacitor, Cavity, Package, and On-Die Capacitance
    14. 8.14 The Fundamental Limits to the Peak Impedance
    15. 8.15 Using One Value MLCC Capacitor on the Board-General Features
    16. 8.16 Optimizing the Single MLCC Capacitance Value
    17. 8.17 Using Three Different Values of MLCC Capacitors on the Board
    18. 8.18 Optimizing the Values of Three Capacitors
    19. 8.19 The Frequency Domain Target Impedance Method (FDTIM) for Selecting Capacitor Values and the Minimum Number of Capacitors
    20. 8.20 Selecting Capacitor Values with the FDTIM
    21. 8.21 When the On-Die Capacitance Is Large and Package Lead Inductance Is Small
    22. 8.22 An Alternative Decoupling Strategy Using Controlled ESR Capacitors
    23. 8.23 On-Package Decoupling (OPD) Capacitors
    24. 8.24 Advanced Section: Impact of Multiple Chips on the Board Sharing the Same Rail
    25. 8.25 The Bottom Line
    26. References
  17. Chapter 9 Transient Currents and PDN Voltage Noise
    1. 9.1   What’s So Important About the Transient Current?
    2. 9.2   A Flat Impedance Profile, a Transient Current, and a Target Impedance
    3. 9.3   Estimating the Transient Current to Calculate the Target Impedance with a Flat Impedance Profile
    4. 9.4   The Actual PDN Current Profile Through a Die
    5. 9.5   Clock-Edge Current When Capacitance Is Referenced to Both Vss and Vdd
    6. 9.6   Measurement Example: Embedded Controller Processor
    7. 9.7   The Real Origin of PDN Noise–How Clock-Edge Current Drives PDN Noise
    8. 9.8   Equations That Govern a PDN Impedance Peak
    9. 9.9   The Most Important Current Waveforms That Characterize the PDN
    10. 9.10 PDN Response to an Impulse of Dynamic Current
    11. 9.11 PDN Response to a Step Change in Dynamic Current
    12. 9.12 PDN Response to a Square Wave of Dynamic Current at Resonance
    13. 9.13 Target Impedance and the Transient and AC Steady-State Responses
    14. 9.14 Impact of Reactive Elements, q-Factor, and Peak Impedances on PDN Voltage Noise
    15. 9.15 Rogue Waves
    16. 9.16 A Robust Design Strategy in the Presence of Rogue Waves
    17. 9.17 Clock-Edge Current Impulses from Switched Capacitor Loads
    18. 9.18 Transient Current Waveforms Composed of a Series of Clock Impulses
    19. 9.19 Advanced Section: Applying Clock Gating, Clock Swallowing, and Power Gating to Real CMOS Situations
    20. 9.20 Advanced Section: Power Gating
    21. 9.21 The Bottom Line
    22. References
  18. Chapter 10 Putting It All Together: A Practical Approach to PDN Design
    1. 10.1 Reiterating Our Goal in PDN Design
    2. 10.2 Summary of the Most Important Power Integrity Principles
    3. 10.3 Introducing a Spreadsheet to Explore Design Space
    4. 10.4 Lines 1–12: PDN Input Voltage, Current, and Target Impedance Parameters
    5. 10.5 Lines 13–24: 0th Dip (Clock-Edge) Noise and On-Die Parameters
    6. 10.6 Extracting the Mounting Inductance and Resistance
    7. 10.7 Analyzing Typical Board and Package Geometries for Inductance
    8. 10.8 The Three Loops of the PDN Resonance Calculator (PRC) Spreadsheet
    9. 10.9 The Performance Figures of Merit
    10. 10.10 Significance of Damping and q-factors
    11. 10.11 Using a Switched Capacitor Load Model to Stimulate the PDN
    12. 10.12 Impulse, Step, and Resonance Response for Three-Peak PDN: Correlation to Transient Simulation
    13. 10.13 Individual q-factors in Both the Frequency and Time Domains
    14. 10.14 Rise Time and Stimulation of Impedance Peak
    15. 10.15 Improvements for a Three-Peak PDN: Reduced Loop Inductance of the Bandini Mountain and Selective MLCC Capacitor Values
    16. 10.16 Improvements for a Three-Peak PDN: A Better SMPS Model
    17. 10.17 Improvements for a Three-Peak PDN: On-Package Decoupling (OPD) Capacitors
    18. 10.18 Transient Response of the PDN: Before and After Improvement
    19. 10.19 Re-examining Transient Current Assumptions
    20. 10.20 Practical Limitations: Risk, Performance, and Cost Tradeoffs
    21. 10.21 Reverse Engineering the PDN Features from Measurements
    22. 10.22 Simulation-to-Measurement Correlation
    23. 10.23 Summary of the Simulated and Measured PDN Impedance and Voltage Features
    24. 10.24 The Bottom Line
    25. References
  19. Index