Overview
The “Power-up” mode (or phase) starts once classification is complete. From the testability point of view, it may be best defined as commencing the moment the port voltage on the PSE-side exceeds 20.5 V, this being the upper limit of the classification range. Several things happen along the way as the port voltage (PI voltage) on the PSE-side rises toward its final settling value. It is clear that this final value is essentially the incoming “48V” rail minus the forward drop across the pass-FET in the PSE. Traditionally, when the port voltage got up very close to its final value, Power-up phase was said to have ended and Power-on achieved. The AT standard, however, laid down one additional qualifying condition before declaring Power-on, ...

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