Improving PCB Thermal Resistance for Exposed Pad Packages
As can be seen from Table 12.1, when talking about packages with exposed pads, we need to refer to JESD51-5 to understand how the standardized 2s2p board is constructed. This would apply typically to PSE chips with integrated (on-chip) pass-FETs in QFN/DFN or even TSSOP packages. The JEDEC standard also specifies that the 2s2p test board size be 76.20 mm × 114.30 mm ± 0.25 mm for packages less than 27 mm on a side. That is 3 in. × 4.5 in., a fairly large board with just one chip being characterized! The standard also recommends the pattern of traces and that a 1-foot square box be used for natural convection measurements as per JESD51-2A.
As per the JEDEC 2s2p board recommendations ...
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