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Power Over Ethernet Interoperability Guide by Sanjaya Maniktala

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The Concept of Creepage
In Fig. 10.5 we established minimum 40 mil for the case of completely coated traces/vias (“nodes”) with a voltage differential of 2.5 kV between them. We also said that it needs to be 60 mil if either or both nodes are not coated. The assumption is that the coating on one node may not be perfect (small pinholes for example), and so if the other node is by design open and exposed, there can be conduction between the two nodes along the surface of the PCB. Current flow along the surface is aided greatly by contaminants (as in condensed water too) present on the surface of the board, and it usually becomes much easier for current to arc over the surface of an insulator rather than through air. Therefore, to avoid this new ...

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