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Power Over Ethernet Interoperability Guide

Book Description

A Complete Guide to Transmitting Electrical Power and Data over Ethernet CablesPower over Ethernet Interoperability explains how to safely transmit DC power over an existing data network cabling structure so that separate AC electrical wiring is not needed to power up devices connected to the network.

Table of Contents

  1. Cover 
  2. About the Author
  3. Title Page
  4. Copyright Page
  5. Contents 
  6. Preface
  7. Acknowledgments
  8. Chapter 1: The Evolution of Power over Ethernet
    1. Part 1: An Overview of Ethernet
      1. Introduction
      2. A Brief History of Ethernet
      3. Modern Three-Layer Hierarchical Network Architecture
      4. What Exactly Is “Ethernet”?
      5. What Is Interoperability?
    2. Part 2: The Historical Evolution of PoE
      1. Introduction
      2. Blasts from the Past
      3. Don’t SWER No More
      4. The Twisted Pair and the Principle of Immunity
      5. Common-Mode Rejection by Coils/Transformers and Other Techniques
      6. Immunity and Emissions
      7. Twist Rate and Wire Diameter
      8. Categories of Ethernet Cable
      9. PoE Cable Categories
      10. Bandwidth and Information Capacity of Cables
      11. Effect of Temperature on Cable Performance
      12. Cable Temperature Rise Caused by PoE
      13. The Center-Tapped (Hybrid) Transformer and the Phantom Circuit
      14. Methods of Injecting PoE via Phantom Power
      15. PoE Chip Vendors: The Emerging Landscape of PoE
  9. Chapter 2: Overview of PoE Implementations
    1. Power Sourcing Equipment and Powered Devices
    2. The Input Voltage Source and Corresponding Power Levels
    3. PoE on Data or Spare Pairs?
    4. Pin Numbering, Colors, and Registered Jacks
    5. Telephone Cable to Ethernet Cable
    6. Midspan or Endspan?
    7. Transmission Lines
    8. Terminations
    9. Types of Powered Devices
  10. Chapter 3: Detection
    1. Overview
    2. Pre-Standard/Legacy Detection Schemes
    3. IEEE Detection
    4. Practical Voltage and Current Limits during Detection
    5. Some Practical Detection Techniques
    6. Predetection/Open-Circuit Detection/Initialization
    7. Detection Back Off
    8. Detection Signature Resistor Disengagement
    9. Lower Detection Threshold: Practical Concerns in PSEs and PDs
  11. Chapter 4: Classification
    1. What Is Classification?
    2. Types of Classification Methods and Backward Compatibility
    3. Practical Limits of AC-DC Power Supplies
    4. Classification Is Optional for Type 1 Application But Recommended
    5. Default Class (Class 0)
    6. LLDP or Physical-Layer Classification for Type 2 PSEs?
    7. Class Levels in Layer-1 Classification
    8. 1-Event Classification
    9. Classification “Gray Areas”
    10. Reported “Interoperability” Issues
    11. Timings during 1-Event Classification
    12. Dissipation during Classification
    13. 2-Event Classification
    14. Timings during 2-Event Classification
    15. Overall Timing Constraints
    16. Multiple-Port Compliance and Systems Issues
    17. Discharging Port Capacitances and Actual Voltage “Seen” by the PD
    18. Detection Signature Resistor Disengagement Concerns
    19. Detection Signature Resistor beyond Detection
    20. IEEE 802.3at Classification Details Summary
    21. IEEE 802.3at Table 33-8 Explained Further
    22. 1-Finger or 2-Finger Classification for Type 2 PSEs?
  12. Chapter 5: Inrush and Power-Up
    1. Overview
    2. Inrush Behavior
    3. Purpose of Inrush Limiting and the PD Bulk Capacitance
    4. Practical PSE Design for Inrush Currents
    5. Undervoltage Lockout Thresholds
    6. Analyzing the Inrush Phase
    7. Ensuring Proper Power-Up Behavior
    8. Testing the Inrush Performance of PSEs
    9. A Discrete PD Front-End for Testing PSEs
    10. The Inrush Timer and the Real End of Inrush
    11. Types of Power-Up Behavior and Power-On
    12. Minimum Inrush Below 30 V
    13. Type 2 PD Delay Timer
    14. Rise-Time Limits
    15. Some Practical PD Design Issues
  13. Chapter 6: Operation
    1. Background
    2. Relevant Sections to Refer To in the AF Standard
    3. Reasons for Protection
    4. Brief Overview of Overloads and Shorts as Per AF Standard
    5. Testing PSE’s Overload and Short-Circuit Protection as Per AF Standard
    6. The Short-Circuit Enigma of the AF (and AT) Standard
    7. Device Dependency in the AF Standard
    8. Evolution of Overload/Short-Circuit Perspective
    9. Short-Circuit Range Comparison (AF and AT)
    10. General Philosophy in Interpreting the AT Standard
    11. Overload and Short-Circuit Requirements as Per AT Standard
    12. Peak Power Calculations
    13. The Recommended Operating Templates Collected and Explained
    14. Some PSE-Controller Design Suggestions for AT Compliance
    15. ICUT Monitoring as Per AT Standard
    16. Current Monitoring and Current Limiting Accuracy
    17. Allowed Port Voltage Sag under Current Limiting
    18. Resumption after “Error” and Timings
    19. Summary of Peak and Operating Values
  14. Chapter 7: Maintain Power and Disconnect
    1. Overview
    2. Keeping the Port Alive
    3. Dropout versus MPS
    4. Setting the Timer for “MPS Valid”
    5. PD Preloading
    6. AC Disconnect and DC Disconnect
    7. Commercial PSE’s Interpretation and Implementation of AC Disconnect
    8. Safety in AC Disconnect
    9. Reasons to Avoid AC Disconnect
  15. Chapter 8: PoE State-Machine Diagrams
  16. Chapter 9: Magnetics
    1. Overview
    2. Open-Circuit Inductance (OCL)
    3. DC-Bias Current Caused by Baseline Wander
    4. Stored Energy and Core Saturation
    5. Resistance Imbalance
    6. “Imbalance” as Per PoE Standards
    7. Current-Imbalance IUNB: What Is It Really?
    8. Worst-Case Imbalances and DC Bias
    9. Derating Power Based on DC-Bias Capability
    10. Ballasting Resistors
    11. EMI Filtering and Common-Mode Filters with PoE
    12. Isolation Requirements in Magnetic Components
    13. Hi-Pot Testing for PoE
    14. Limits on the Y-Capacitance in Magjacks
    15. Vendors Cheating on Y-caps—to Our Advantage
  17. Chapter 10: Isolation, PCB Design, and Safety
    1. Safety Standards Overview
    2. PoE and Safety
    3. Steady and Transient Voltages
    4. Fault Conditions
    5. PoE Rails, Ethernet/Telecom Systems
    6. Isolation Requirements
    7. The PoE Hi-Pot Test
    8. Failing the Hi-Pot Test
    9. Separation Anxiety
    10. Causes of Isolation Breakdown and Recommended Minimum Clearance
    11. Summarizing Recommendations for Minimum Clearance
    12. The Concept of Creepage
    13. Coating versus Noncoating
    14. Separations in Inner Layers
    15. Minimum Vertical Separation in PCB
    16. Secondary Discharge
    17. PD Isolation Requirements
    18. Higher Surge, Cable ESD, and Reliability
    19. Limited Power Source
  18. Chapter 11: Surge Testing and Protection
    1. Overview
    2. Mandatory versus Custom-Driven Requirements
    3. Template for Testing during PoE Design Qualification Phase
    4. Recommended Surge Test Setup
    5. What Happens during the Surge Test
    6. Other Setups for Surge Testing
    7. Modeling the Combination Wave Generator (CWG)
    8. Recommendations for AC Disconnect
    9. Recommendations for Common-Mode Filter Position
    10. Recommendations for DC Disconnect
    11. Surviving the 10/700-μs Surge Test
    12. Protecting the PD from Surges
    13. Semiconductors for Protection and Some PCB Recommendations
    14. PoE Is an Intrabuilding Standard
    15. GR-1089 (Telcordia) Requirements
    16. ESD Protection of ICs
    17. Cable ESD (CDE)
    18. Port Protection Diode in PoE: Any TVS Required?
    19. Should D1 Be a TVS?
    20. Appendix: Modeling and Analysis of the Combination-Wave Generator Used for Surge Testing (EN 61000-4-5)
  19. Chapter 12: Lab Skills, Thermal Management, and Decoupling
    1. Using Oscilloscopes Wisely (in PoE)
    2. Measuring PSE Port Voltage
    3. Earth Ground Loop Issue and Isolating the Oscilloscope
    4. Thermal Management
    5. The JEDEC Standards (JESD)
    6. Types of Test Boards
    7. Improving PCB Thermal Resistance for Exposed Pad Packages
    8. Practical Thermal Resistances
    9. Sizing Copper Traces
    10. Calculating Junction Temperature
    11. Different Ways of Specifying Maximum Operating Temperature
    12. Fan Speed
    13. Proper Chip Decoupling
  20. Chapter 13: N-Pair Power Delivery Systems
    1. Overview
    2. Starting with Resistance
    3. Loop Resistances for N-Pair Power Delivery
    4. Power Estimates for N-Pair Power Delivery
    5. Maximum Power Delivery over Long Distances Using Available PSEs
    6. Impedance Matching for Maximum Power Delivery
    7. The Power Delivery Problem
    8. Mathematical Solution
    9. Lowering the PD Undervoltage Lockout
    10. Plotting Power Delivery Curves over Long Distances
    11. Sample Numerical Calculations for N-Power Delivery
    12. How Far Will a Given PD Operate?
    13. Learning from Telephony
    14. Four-Pair Implementations
    15. Future Innovation
  21. Chapter 14: Auxiliary Power and Flyback Design
    1. Overview
    2. Auxiliary Power Option A (Front Aux or FAUX Pin Method)
    3. Auxiliary Power Option B (Rear Aux or RAUX Pin Method)
  22. Index