O'Reilly logo

PCI Express System Architecture by MindShare, Inc, Ravi Budruk, Don Anderson, Tom Shanley

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

Link Active State Power Management

PCI Express includes a feature that requires link power conservation even though the device has not been placed in a low-power state by software. Consequently this feature is call “Active State” power management and functions only when the device is in the DO state. Transitions into and out of Active State Power Management (ASPM) are handled solely by Hardware.

Two low power states are defined for ASPM:

  1. L0 standby (L0s) — this state is required by all PCI Express devices and applies to a single direction on the link. The latency to return to the L0 state is specified to be very short.

  2. L1 ASPM — this state is optional and can be entered to achieve a greater degree of power conservation than L0s. This state also ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required