LTSSM Related Configuration Registers
Only those bits associated with the Link Training and Initialization state are described here.
Link Capability Register
The Link Capability Register is pictured in Figure 14-21 on page 550 and each bit field is described in the subsections that follow.
Figure 14-21. Link Capabilities Register
Maximum Link Speed[3:0]
This bit must currently be hard-wired to 0001b, indicating that its supported speed is the Generation 1 Link speed of 2.5Gbits/s. All other encodings are reserved.
Maximum Link Width[9:4]
This field indicates the maximum width of the PCI Express Link. The values that are defined are:
000000b: Reserved. ...
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