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PCI Express System Architecture

Book Description

Mindshare presents a book on the newest bus architecture, PCI Express.

  • PCI EXPRESS is considered to be the most general purpose bus so it should appeal to a wide audience in this arena.

  • Today's buses are becoming more specialized to meet the needs of the particular system applications, building the need for this book.

  • Mindshare and their only competitor in this space team up in this new book.

  • Table of Contents

    1. Copyright
    2. Figures
    3. Tables
    4. Acknowledgments
    5. About This Book
    6. The Big Picture
      1. Architectural Perspective
        1. This Chapter
        2. The Next Chapter
        3. Introduction To PCI Express
        4. Predecessor Buses Compared
        5. I/O Bus Architecture Perspective
        6. The PCI Express Way
        7. PCI Express Specifications
      2. Architecture Overview
        1. Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction to PCI Express Transactions
        5. PCI Express Device Layers
        6. Example of a Non-Posted Memory Read Transaction
        7. Hot Plug
        8. PCI Express Performance and Data Transfer Efficiency
    7. Transaction Protocol
      1. Address Spaces & Transaction Routing
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction
        5. Two Types of Local Link Traffic
        6. Transaction Layer Packet Routing Basics
        7. Applying Routing Mechanisms
        8. Plug-And-Play Configuration of Routing Options
      2. Packet-Based Transactions
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction to the Packet-Based Protocol
        5. Transaction Layer Packets
        6. Data Link Layer Packets
      3. ACK/NAK Protocol
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Reliable Transport of TLPs Across Each Link
        5. Elements of the ACK/NAK Protocol
        6. ACK/NAK DLLP Format
        7. ACK/NAK Protocol Details
        8. Error Situations Reliably Handled by ACK/NAK Protocol
        9. ACK/NAK Protocol Summary
        10. Recommended Priority To Schedule Packets
        11. Some More Examples
        12. Switch Cut-Through Mode
      4. QoS/TCs/VCs and Arbitration
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Quality of Service
        5. Perspective on QOS/TC/VC and Arbitration
        6. Traffic Classes and Virtual Channels
        7. Arbitration
      5. Flow Control
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Flow Control Concept
        5. Flow Control Buffers
        6. Introduction to the Flow Control Mechanism
        7. Flow Control Packets
        8. Operation of the Flow Control Model - An Example
        9. Infinite Flow Control Advertisement
        10. The Minimum Flow Control Advertisement
        11. Flow Control Initialization
        12. Flow Control Updates Following FC_INIT
      6. Transaction Ordering
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction
        5. Producer/Consumer Model
        6. Native PCI Express Ordering Rules
        7. Relaxed Ordering
        8. Modified Ordering Rules Improve Performance
        9. Support for PCI Buses and Deadlock Avoidance
      7. Interrupts
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Two Methods of Interrupt Delivery
        5. Message Signaled Interrupts
        6. Legacy PCI Interrupt Delivery
        7. Devices May Support Both MSI and Legacy Interrupts
        8. Special Consideration for Base System Peripherals
      8. Error Detection and Handling
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Background
        5. Introduction to PCI Express Error Management
        6. Sources of PCI Express Errors
        7. Error Classifications
        8. How Errors are Reported
        9. Baseline Error Detection and Handling
        10. Advanced Error Reporting Mechanisms
        11. Summary of Error Logging and Reporting
    8. The Physical Layer
      1. Physical Layer Logic
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Physical Layer Overview
        5. Transmit Logic Details
        6. Receive Logic Details
        7. Physical Layer Error Handling
      2. Electrical Physical Layer
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Electrical Physical Layer Overview
        5. High Speed Electrical Signaling
        6. LVDS Eye Diagram
        7. Transmitter Driver Characteristics
        8. Input Receiver Characteristics
        9. Electrical Physical Layer State in Power States
      3. System Reset
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Two Categories of System Reset
        5. Reset Exit
        6. Link Wakeup from L2 Low Power State
      4. Link Initialization & Training
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Link Initialization and Training Overview
        5. Ordered-Sets Used During Link Training and Initialization
        6. Link Training and Status State Machine (LTSSM)
        7. Detailed Description of LTSSM States
        8. LTSSM Related Configuration Registers
    9. Power-Related Topics
      1. Power Budgeting
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction to Power Budgeting
        5. The Power Budgeting Elements
        6. Slot Power Limit Control
        7. The Power Budget Capabilities Register Set
      2. Power Management
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction
        5. Primer on Configuration Software
        6. Function Power Management
        7. Introduction to Link Power Management
        8. Link Active State Power Management
        9. Software Initiated Link Power Management
        10. Link Wake Protocol and PME Generation
    10. Optional Topics
      1. Hot Plug
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Background
        5. Hot Plug in the PCI Express Environment
        6. Elements Required to Support Hot Plug
        7. Card Removal and Insertion Procedures
        8. Standardized Usage Model
        9. Standard Hot Plug Controller Signaling Interface
        10. The Hot-Plug Controller Programming Interface
        11. Slot Numbering
        12. Quiescing Card and Driver
        13. The Primitives
      2. Add-in Cards and Connectors
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction
        5. Form Factors Under Development
    11. PCI Express Configuration
      1. Configuration Overview
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Definition of Device and Function
        5. Definition of Primary and Secondary Bus
        6. Topology Is Unknown At Startup
        7. Each Function Implements a Set of Configuration Registers
        8. Host/PCI Bridge's Configuration Registers
        9. Configuration Transactions Are Originated by the Processor
        10. Configuration Transactions Are Routed Via Bus, Device, and Function Number
        11. How a Function Is Discovered
        12. How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Function
      2. Configuration Mechanisms
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction
        5. PCI-Compatible Configuration Mechanism
        6. PCI Express Enhanced Configuration Mechanism
        7. Type 0 Configuration Request
        8. Type 1 Configuration Request
        9. Example PCI-Compatible Configuration Access
        10. Example Enhanced Configuration Access
        11. Initial Configuration Accesses
      3. PCI Express Enumeration
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Introduction
        5. Enumerating a System With a Single Root Complex
        6. Enumerating a System With Multiple Root Complexes
        7. A Multifunction Device Within a Root Complex or a Switch
        8. An Endpoint Embedded in a Switch or Root Complex
        9. Memorize Your Identity
        10. Root Complex Register Blocks (RCRBs)
        11. Miscellaneous Rules
      4. PCI Compatible Configuration Registers
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. Header Type 0
        5. Header Type 1
        6. PCI-Compatible Capabilities
      5. Expansion ROMs
        1. The Previous Chapter
        2. This Chapter
        3. The Next Chapter
        4. ROM Purpose—Device Can Be Used In Boot Process
        5. ROM Detection
        6. ROM Shadowing Required
        7. ROM Content
        8. Execution of Initialization Code
        9. Introduction to Open Firmware
      6. Express-Specific Configuration Registers
        1. The Previous Chapter
        2. This Chapter
        3. Introduction
        4. PCI Express Capability Register Set
        5. PCI Express Extended Capabilities
        6. RCRB
    12. Appendices
      1. Test, Debug and Verification
        1. Scope
        2. Serial Bus Topology
        3. Dual-Simplex
        4. Setting Up the Analyzer, Capturing and Triggering
        5. Link Training, the First Step in Communication
        6. Slot Connector vs. Mid-Bus Pad
        7. Exercising: In-Depth Verification
        8. Signal Integrity, Design and Measurement
      2. Markets & Applications for the PCI Express™ Architecture
        1. Introduction
        2. Enterprise Computing Systems
        3. Embedded Control
        4. Storage Systems
        5. Communications Systems
        6. Summary
      3. Implementing Intelligent Adapters and Multi-Host Systems With PCI Express™ Technology
        1. Introduction
        2. Usage Models
        3. The History Multi-Processor Implementations Using PCI
        4. Implementing Multi-host/Intelligent Adapters in PCI Express Base Systems
        5. Summary
        6. Address Translation
      4. Class Codes
      5. Locked Transactions Series
        1. Introduction
        2. Background
        3. The PCI Express Lock Protocol
        4. Summary of Locking Rules
    13. Index