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Parallel Computer Organization and Design

Book Description

Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software.

Table of Contents

  1. Cover
  2. Half Title
  3. Title Page
  4. Copyright
  5. Contents
  6. Preface
  7. 1. Introduction
    1. 1.1 What is computer architecture?
    2. 1.2 Components of a parallel architecture
    3. 1.3 Parallelism in architectures
    4. 1.4 Performance
    5. 1.5 Technological challenges
    6. Exercises
  8. 2. Impact of technology
    1. 2.1 Chapter overview
    2. 2.2 Basic laws of electricity
    3. 2.3 The MOSFET transistor and CMOS inverter
    4. 2.4 Technology scaling
    5. 2.5 Power and energy
    6. 2.6 Reliability
    7. Exercises
  9. 3. Processor microarchitecture
    1. 3.1 Chapter overview
    2. 3.2 Instruction set architecture
    3. 3.3 Statically scheduled pipelines
    4. 3.4 Dynamically scheduled pipelines
    5. 3.5 VLIW microarchitectures
    6. 3.6 EPIC microarchitectures
    7. 3.7 Vector microarchitectures
    8. Exercises
  10. 4. Memory hierarchies
    1. 4.1 Chapter overview
    2. 4.2 The pyramid of memory levels
    3. 4.3 Cache hierarchy
    4. 4.4 Virtual memory
    5. Exercises
  11. 5. Multiprocessor systems
    1. 5.1 Chapter overview
    2. 5.2 Parallel-programming model abstractions
    3. 5.3 Message-passing multiprocessor systems
    4. 5.4 Bus-based shared-memory systems
    5. 5.5 Scalable shared-memory systems
    6. 5.6 Cache-only shared-memory systems
    7. Exercises
  12. 6. Interconnection networks
    1. 6.1 Chapter overview
    2. 6.2 Design space of interconnection networks
    3. 6.3 Switching strategies
    4. 6.4 Topologies
    5. 6.5 Routing techniques
    6. 6.6 Switch architecture
    7. Exercises
  13. 7. Coherence, synchronization, and memory consistency
    1. 7.1 Chapter overview
    2. 7.2 Background
    3. 7.3 Coherence and store atomicity
    4. 7.4 Sequential consistency
    5. 7.5 Synchronization
    6. 7.6 Relaxed memory-consistency models
    7. 7.7 Speculative violations of memory orders
    8. Exercises
  14. 8. Chip multiprocessors
    1. 8.1 Chapter overview
    2. 8.2 Rationale behind CMPs
    3. 8.3 Core multi-threading
    4. 8.4 Chip multiprocessor architectures
    5. 8.5 Programming models
    6. Exercises
  15. 9. Quantitative evaluations
    1. 9.1 Chapter overview
    2. 9.2 Taxonomy of simulators
    3. 9.3 Integrating simulators
    4. 9.4 Multiprocessor simulators
    5. 9.5 Power and thermal simulations
    6. 9.6 Workload sampling
    7. 9.7 Workload characterization
    8. Exercises
  16. Index