On-Chip Communication Architectures

Chapter 11. Physical Design Trends for Interconnects

Ioannis Savidis and Eby G. Friedman

Over the past 10 years, the source of the critical signal delays has undergone a major transition. With the scaling of active device feature sizes into the deep submicrometer (DSM) regime, the on-chip interconnect has become the primary bottleneck in signal flow within high complexity, high speed integrated circuits (ICs). The smaller feature size in DSM technology nodes reduces the delay of the active devices; however, the effect on delay due to the passive interconnects has increased rapidly, as described by the 2005 International Technology Roadmap for Semiconductors (ITRS) [1]. The transition from an IC dominated by gate delays for feature sizes greater ...