On-Chip Communication Architectures

Chapter 9. On-Chip Communication Architecture Refinement and Interface Synthesis

In a typical SoC design flow, several models of the system are created that capture different levels of detail, for different purposes. Figure 9.1 shows how communication architecture refinement and interface synthesis involve transformations between models with different levels of detail, in a typical design flow. Functional (or task/process graph) level models focus on capturing the functionality of the system, without any notion of hardware or software components that will ultimately implement the functionality. Such models are typically used as “golden reference” models to allow later stages of the design flow to check and validate the intended functionality of ...