Book description
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
- A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
- Detailed analysis of all popular standards for on-chip communication architectures
- Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
- Future trends that with have a significant impact on research and design of communication architectures over the next several years
Table of contents
- Copyright
- The Morgan Kaufmann Series in Systems on Silicon
- Preface
- About the Authors
- Acknowledgments
- List of Contributors
- 1. Introduction
- 2. Basic Concepts of Bus-Based Communication Architectures
-
3. On-Chip Communication Architecture Standards
- 3.1. Standard On-Chip Bus-Based Communication Architectures
- 3.2. Socket-Based On-Chip Bus Interface Standards
- 3.3. Discussion: Off-Chip Bus Architecture Standards
- 3.4. Summary
-
References
-
4. Models for Performance Exploration
- 4.1. Static Performance Estimation Models
- 4.2. Dynamic (Simulation-Based) Performance Estimation Models
- 4.3. Hybrid Communication Architecture Performance Estimation Approaches
- 4.4. Summary
-
References
- 5. Models for Power and Thermal Estimation
-
6. Synthesis of On-Chip Communication Architectures
- 6.1. Bus Topology Synthesis
- 6.2. Bus Protocol Parameter Synthesis
- 6.3. Bus Topology and Protocol Parameter Synthesis
- 6.4. Physical Implementation Aware Synthesis
- 6.5. Memory–Communication Architecture Co-Synthesis
- 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures
- 6.7. Summary
-
References
- 7. Encoding Techniques for On-Chip Communication Architectures
- 8. Custom Bus-Based On-Chip Communication Architecture Design
- 9. On-Chip Communication Architecture Refinement and Interface Synthesis
- 10. Verification and Security Issues in On-Chip Communication Architecture Design
- 11. Physical Design Trends for Interconnects
- 12. Networks-On-Chip
- 13. Emerging On-Chip Interconnect Technologies
Product information
- Title: On-Chip Communication Architectures
- Author(s):
- Release date: July 2010
- Publisher(s): Morgan Kaufmann
- ISBN: 9780080558288
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