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On-Chip Communication Architectures

Book Description

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

Table of Contents

  1. Copyright
  2. The Morgan Kaufmann Series in Systems on Silicon
  3. Preface
    1. Audience for this Book
    2. How to Use this Book
  4. About the Authors
  5. Acknowledgments
  6. List of Contributors
  7. 1. Introduction
    1. 1.1. Trends in System-On-Chip Design
    2. 1.2. Coping with SoC Design Complexity
    3. 1.3. ESL Design Flow
    4. 1.4. On-Chip Communication Architectures: A Quick Look
      1. 1.4.1. Types of On-Chip Communication Architectures
      2. 1.4.2. Impact of Increasing Application Complexity
      3. 1.4.3. Impact of Technology Scaling
    5. 1.5. Book Outline
    6. References
  8. 2. Basic Concepts of Bus-Based Communication Architectures
    1. 2.1. Terminology
    2. 2.2. Characteristics of Bus-Based Communication Architectures
      1. 2.2.1. Bus Signal Types
      2. 2.2.2. Physical Structure
      3. 2.2.3. Clocking
      4. 2.2.4. Decoding
      5. 2.2.5. Arbitration
    3. 2.3. Data Transfer Modes
      1. 2.3.1. Single Non-pipelined Transfer
      2. 2.3.2. Pipelined Transfer
      3. 2.3.3. Burst Transfer
      4. 2.3.4. Split Transfer
      5. 2.3.5. Out-of-Order Transfer
      6. 2.3.6. Broadcast Transfer
    4. 2.4. Bus Topology Types
    5. 2.5. Physical Implementation of Bus Wires
    6. 2.6. Discussion: Buses in the DSM ERA
    7. 2.7. Summary
    8. References
  9. 3. On-Chip Communication Architecture Standards
    1. 3.1. Standard On-Chip Bus-Based Communication Architectures
      1. 3.1.1. AMBA 2.0
        1. 3.1.1.1. Advanced High Performance Bus
          1. AHB Bus Matrix Topology
        2. 3.1.1.2. Advanced Peripheral Bus
      2. 3.1.2. AMBA 3.0
        1. 3.1.2.1. Advanced Exensible Interface
          1. AXI Bus Matrix Topology
      3. 3.1.3. IBM CoreConnect
        1. 3.1.3.1. Processor Local Bus
        2. 3.1.3.2. On-Chip Peripheral Bus
        3. 3.1.3.3. Device Control Register Bus
      4. 3.1.4. STMicroelectronics STBus
        1. 3.1.4.1. Type 1
        2. 3.1.4.2. Type 2
        3. 3.1.4.3. Type 3
        4. 3.1.4.4. STBus Components
      5. 3.1.5. Sonics SMART Interconnect
        1. 3.1.5.1. SonicsMX
        2. 3.1.5.2. SonicsLX
        3. 3.1.5.3. Sonics Synapse 3220
      6. 3.1.6. OpenCores Wishbone
      7. 3.1.7. Altera Avalon
        1. 3.1.7.1. Avalon-MM
        2. 3.1.7.2. Avalon-ST
    2. 3.2. Socket-Based On-Chip Bus Interface Standards
      1. 3.2.1. Open Core Protocol
        1. 3.2.1.1. OCP Signals
        2. 3.2.1.2. OCP Profiles
      2. 3.2.2. VSIA Virtual Component Interface
      3. 3.2.3. Philips Device Transaction Level Protocol
    3. 3.3. Discussion: Off-Chip Bus Architecture Standards
    4. 3.4. Summary
      1. Brief Discussion: Evolution of On-Chip Communication Protocols
    5. References
  10. 4. Models for Performance Exploration
    1. 4.1. Static Performance Estimation Models
      1. 4.1.1. Early Work
      2. 4.1.2. Protocol Delay-Aware Approach
      3. 4.1.3. AMBA 2.0 AHB Estimation
      4. 4.1.4. Discussion: Limitations of Static Performance Estimation Methods
    2. 4.2. Dynamic (Simulation-Based) Performance Estimation Models
      1. 4.2.1. Cycle Accurate Models
      2. 4.2.2. Pin-Accurate Bus Cycle Accurate Models
      3. 4.2.3. Transaction-Based Bus Cycle Accurate Models
        1. 4.2.3.1. Communication Architecture Exploration with T-BCA Models
        2. 4.2.3.2. The CCATB Approach
      4. 4.2.4. Transaction Level Models (TLM)
      5. 4.2.5. Multiple Abstraction Modeling Flows
        1. 4.2.5.1. Layered Abstraction Approaches
    3. 4.3. Hybrid Communication Architecture Performance Estimation Approaches
      1. 4.3.1. Trace-Based Approach
      2. 4.3.2. Queuing Theory-Based Approach
    4. 4.4. Summary
    5. References
  11. 5. Models for Power and Thermal Estimation
    1. 5.1. Bus Wire Power Models
      1. 5.1.1. Early Work
      2. 5.1.2. Coupling-Aware Power Models
      3. 5.1.3. High Level Power Models
        1. 5.1.3.1. Switching Power
        2. 5.1.3.2. Power Due to Vias
        3. 5.1.3.3. Power Due to Repeaters
    2. 5.2. Comprehensive Bus Architecture Power Models
      1. 5.2.1. Macro-Models for Bus Matrix Communication Architectures
        1. 5.2.1.1. Input Stage
        2. 5.2.1.2. Decoder
        3. 5.2.1.3. Output Stage
        4. 5.2.1.4. Arbiter
        5. 5.2.1.5. Bus Wires
      2. 5.2.2. Other Macro-Model-Based Techniques
    3. 5.3. Bus Wire Thermal Models
    4. 5.4. Discussion: PVT Variation-Aware Power Estimation
    5. 5.5. Summary
    6. References
  12. 6. Synthesis of On-Chip Communication Architectures
    1. 6.1. Bus Topology Synthesis
      1. 6.1.1. Hierarchical Bus Architecture Topology Synthesis
      2. 6.1.2. Bus Matrix (or Crossbar) Topology Synthesis
      3. 6.1.3. Summary of Other Topology Synthesis Research
    2. 6.2. Bus Protocol Parameter Synthesis
      1. 6.2.1. Component Mapping and Protocol Parameter Synthesis
      2. 6.2.2. Arbitration Scheme Synthesis
    3. 6.3. Bus Topology and Protocol Parameter Synthesis
      1. 6.3.1. Hierarchical Shared Bus Topology and Protocol Parameter Synthesis
      2. 6.3.2. Bus Matrix Topology and Protocol Parameter Synthesis
    4. 6.4. Physical Implementation Aware Synthesis
      1. 6.4.1. Fabsyn: Physically Aware Hierarchical Shared Bus Architecture Synthesis
    5. 6.5. Memory–Communication Architecture Co-Synthesis
      1. 6.5.1. Early Work
      2. 6.5.2. COSMECA Co-synthesis Approach
      3. 6.5.3. Other Co-synthesis Approach
    6. 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures
      1. 6.6.1. Performance Optimizations
      2. 6.6.2. Power Optimizations
    7. 6.7. Summary
    8. References
  13. 7. Encoding Techniques for On-Chip Communication Architectures
    1. 7.1. Techniques for Power Reduction
      1. 7.1.1. Schemes for Reducing Self-Switching Power
        1. 7.1.1.1. Address Buses
        2. 7.1.1.2. Data Buses
        3. 7.1.1.3. Serial Buses
      2. 7.1.2. Schemes for Reducing Coupling Power
        1. 7.1.2.1. Address Buses
        2. 7.1.2.2. Data Buses
    2. 7.2. Techniques for Reducing Capacitive Crosstalk Delay
    3. 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects
    4. 7.4. Techniques for Reducing Inductive Crosstalk Effects
    5. 7.5. Techniques for Fault Tolerance and Reliability
    6. 7.6. Summary
    7. References
  14. 8. Custom Bus-Based On-Chip Communication Architecture Design
    1. 8.1. Split Bus Architectures
    2. 8.2. Serial Bus Architectures
    3. 8.3. CDMA-Based Bus Architectures
    4. 8.4. Asynchronous Bus Architectures
    5. 8.5. Dynamically Reconfigurable Bus Architectures
      1. 8.5.1. Dynamic Bus Architecture Parameter Reconfiguration
        1. 8.5.1.1. Communication Architecture Tuners
        2. 8.5.1.2. LOTTERYBUS
        3. 8.5.1.3. Other Dynamic Parameter Adaptation Schemes
      2. 8.5.2. Dynamic Bus Architecture Topology Reconfiguration
    6. 8.6. Summary
    7. Further Reading
    8. References
  15. 9. On-Chip Communication Architecture Refinement and Interface Synthesis
    1. 9.1. On-Chip Communication Architecture Refinement
      1. 9.1.1. COSY Methodology
      2. 9.1.2. SpecC Methodology
      3. 9.1.3. Coral Framework
    2. 9.2. Interface Synthesis
      1. 9.2.1. Connecting Components at Different Abstraction Levels
        1. 9.2.1.1. TIMA Approach
      2. 9.2.2. Connecting Mismatched Protocols
        1. 9.2.2.1. Early Work
        2. 9.2.2.2. Addressing Protocol Mismatches for Interface Standards
          1. Bridge Protocol Converters
          2. Component Interface Protocol Converters
          3. An Example of Protocol Conversion Using Petri Nets
      3. 9.2.3. Interface Optimization
        1. 9.2.3.1. Interface Pre-Fetching
    3. 9.3. Discussion: Interface Synthesis
    4. 9.4. Summary
    5. References
  16. 10. Verification and Security Issues in On-Chip Communication Architecture Design
    1. 10.1. Verification of On-Chip Communication Protocols
      1. 10.1.1. Early Work with PCI Bus Protocol Verification
      2. 10.1.2. Verifying On-Chip Communication Architectures
    2. 10.2. Compliance Verification for IP Block Integration
      1. 10.2.1. Dynamic Simulation-Based Techniques
      2. 10.2.2. Static Formal Verification-Based Techniques
    3. 10.3. Basic Concepts of SoC Security
    4. 10.4. Security Support in Standard Bus Protocols
    5. 10.5. Communication Architecture Enhancements for Improving SoC Security
    6. 10.6. Summary
    7. References
  17. 11. Physical Design Trends for Interconnects
    1. 11.1. DSM Interconnect Design
    2. 11.2. Low Power, High Speed Circuit Design Techniques
      1. 11.2.1. CMOS Power Dissipation
      2. 11.2.2. Wire Sizing
      3. 11.2.3. Driver Sizing
      4. 11.2.4. Tapered Buffers
      5. 11.2.5. Repeater Insertion
      6. 11.2.6. Summary
    3. 11.3. Global Power Distribution Networks
      1. 11.3.1. Noise in Power Distribution Networks
      2. 11.3.2. Multi-Path Current Redistribution
      3. 11.3.3. Electromigration
      4. 11.3.4. Summary
    4. 11.4. Clock Distribution Networks
      1. 11.4.1. Timing Relationships
      2. 11.4.2. Clock Network Topologies
      3. 11.4.3. Asymmetric Topologies
      4. 11.4.4. Symmetric Topologies
      5. 11.4.5. Power Considerations
      6. 11.4.6. Summary
    5. 11.5. 3-D Interconnects
    6. 11.6. Summary and Concluding Remarks
    7. References
  18. 12. Networks-On-Chip
    1. 12.1. Network Topology
      1. 12.1.1. Direct Networks
      2. 12.1.2. Indirect Networks
      3. 12.1.3. Irregular Networks
    2. 12.2. Switching Strategies
      1. 12.2.1. Circuit Switching
      2. 12.2.2. Packet Switching
    3. 12.3. Routing Algorithms
    4. 12.4. Flow Control
      1. 12.4.1. Data Link-Layer Flow Control
        1. 12.4.1.1. STALL/GO
        2. 12.4.1.2. T-Error
        3. 12.4.1.3. ACK/NACK
      2. 12.4.2. Network and Transport-Layer Flow Control
        1. 12.4.2.1. Flow Control without Resource Reservation
        2. 12.4.2.2. Flow Control with Resource Reservation
    5. 12.5. Clocking Schemes
    6. 12.6. Quality of Service
    7. 12.7. NoC Architectures
      1. 12.7.1. Æthereal
      2. 12.7.2. HERMES
      3. 12.7.3. MANGO
      4. 12.7.4. Nostrum
      5. 12.7.5. Octagon
      6. 12.7.6. QNoC
      7. 12.7.7. SOCBUS
      8. 12.7.8. SPIN
      9. 12.7.9. Xpipes
    8. 12.8. NoC Status and Open Problems
    9. 12.9. Summary
    10. Further Reading
    11. References
  19. 13. Emerging On-Chip Interconnect Technologies
    1. 13.1. Optical Interconnects
      1. 13.1.1. Use of OIs for On-Chip Communication
    2. 13.2. RF/Wireless Interconnects
      1. 13.2.1. Use of RF/Wireless Interconnects for On-Chip Communication
    3. 13.3. CNT Interconnects
      1. 13.3.1. Circuit Parameters for Isolated SWCNTS
      2. 13.3.2. Circuit Parameters for a Bundle of SWCNTs
      3. 13.3.3. Comparison between Copper and SWCNT-Bundles
      4. 13.3.4. Multi-Wall Carbon Nanotubes (MWCNT)
      5. 13.3.5. Using CNTs for On-Chip Communication
    4. 13.4. Summary
    5. References